|uart_regs
clk => clk~0.IN2
wb_rst_i => wb_rst_i~0.IN2
wb_addr_i[0] => Mux7.IN6
wb_addr_i[0] => Mux6.IN6
wb_addr_i[0] => Mux5.IN7
wb_addr_i[0] => Mux4.IN6
wb_addr_i[0] => Mux3.IN7
wb_addr_i[0] => Mux2.IN7
wb_addr_i[0] => Mux1.IN7
wb_addr_i[0] => Mux0.IN7
wb_addr_i[0] => Equal0.IN0
wb_addr_i[0] => Equal1.IN2
wb_addr_i[0] => Equal2.IN2
wb_addr_i[0] => Equal3.IN0
wb_addr_i[0] => Equal4.IN0
wb_addr_i[0] => Equal5.IN0
wb_addr_i[1] => Mux7.IN5
wb_addr_i[1] => Mux6.IN5
wb_addr_i[1] => Mux5.IN6
wb_addr_i[1] => Mux4.IN5
wb_addr_i[1] => Mux3.IN6
wb_addr_i[1] => Mux2.IN6
wb_addr_i[1] => Mux1.IN6
wb_addr_i[1] => Mux0.IN6
wb_addr_i[1] => Equal0.IN2
wb_addr_i[1] => Equal1.IN0
wb_addr_i[1] => Equal2.IN1
wb_addr_i[1] => Equal3.IN1
wb_addr_i[1] => Equal4.IN2
wb_addr_i[1] => Equal5.IN1
wb_addr_i[2] => Mux7.IN4
wb_addr_i[2] => Mux6.IN4
wb_addr_i[2] => Mux5.IN5
wb_addr_i[2] => Mux4.IN4
wb_addr_i[2] => Mux3.IN5
wb_addr_i[2] => Mux2.IN5
wb_addr_i[2] => Mux1.IN5
wb_addr_i[2] => Mux0.IN5
wb_addr_i[2] => Equal0.IN1
wb_addr_i[2] => Equal1.IN1
wb_addr_i[2] => Equal2.IN0
wb_addr_i[2] => Equal3.IN2
wb_addr_i[2] => Equal4.IN1
wb_addr_i[2] => Equal5.IN2
wb_dat_i[0] => wb_dat_i[0]~7.IN1
wb_dat_i[1] => wb_dat_i[1]~6.IN1
wb_dat_i[2] => wb_dat_i[2]~5.IN1
wb_dat_i[3] => wb_dat_i[3]~4.IN1
wb_dat_i[4] => wb_dat_i[4]~3.IN1
wb_dat_i[5] => wb_dat_i[5]~2.IN1
wb_dat_i[6] => wb_dat_i[6]~1.IN1
wb_dat_i[7] => wb_dat_i[7]~0.IN1
wb_dat_o[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
wb_dat_o[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
wb_dat_o[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
wb_dat_o[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
wb_dat_o[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
wb_dat_o[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
wb_dat_o[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
wb_dat_o[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
wb_we_i => lcr[7].CLK
wb_we_i => lcr[6].CLK
wb_we_i => lcr[5].CLK
wb_we_i => lcr[4].CLK
wb_we_i => lcr[3].CLK
wb_we_i => lcr[2].CLK
wb_we_i => lcr[1].CLK
wb_we_i => lcr[0].CLK
wb_we_i => ier[3].CLK
wb_we_i => ier[2].CLK
wb_we_i => ier[1].CLK
wb_we_i => ier[0].CLK
wb_we_i => dl[15].CLK
wb_we_i => dl[14].CLK
wb_we_i => dl[13].CLK
wb_we_i => dl[12].CLK
wb_we_i => dl[11].CLK
wb_we_i => dl[10].CLK
wb_we_i => dl[9].CLK
wb_we_i => dl[8].CLK
wb_we_i => fcr[1].CLK
wb_we_i => fcr[0].CLK
wb_we_i => rx_reset.CLK
wb_we_i => tx_reset.CLK
wb_we_i => scratch[7].CLK
wb_we_i => scratch[6].CLK
wb_we_i => scratch[5].CLK
wb_we_i => scratch[4].CLK
wb_we_i => scratch[3].CLK
wb_we_i => scratch[2].CLK
wb_we_i => scratch[1].CLK
wb_we_i => scratch[0].CLK
wb_we_i => dl[7].CLK
wb_we_i => dl[6].CLK
wb_we_i => dl[5].CLK
wb_we_i => dl[4].CLK
wb_we_i => dl[3].CLK
wb_we_i => dl[2].CLK
wb_we_i => dl[1].CLK
wb_we_i => dl[0].CLK
wb_we_i => start_dlc.CLK
wb_we_i => fifo_write~0.IN1
wb_re_i => fifo_read~0.IN1
wb_re_i => iir_read~0.IN0
wb_re_i => lsr_mask_condition~0.IN0
stx_pad_o <= uart_transmitter:transmitter.port6
srx_pad_i => serial_delay.DATAIN
mc_cs3 => always9~0.IN1
mc_cs3 => always8~0.IN0
mc_cs3 => always7~0.IN0
mc_cs3 => always6~0.IN0
mc_cs3 => always5~0.IN0
int_o <= int_o~reg0.DB_MAX_OUTPUT_PORT_TYPE


|uart_regs|uart_transmitter:transmitter
clk => clk~0.IN1
wb_rst_i => tstate[2]~reg0.ACLR
wb_rst_i => tstate[1]~reg0.ACLR
wb_rst_i => tstate[0]~reg0.ACLR
wb_rst_i => stx_o_tmp.PRESET
wb_rst_i => counter[4].ACLR
wb_rst_i => counter[3].ACLR
wb_rst_i => counter[2].ACLR
wb_rst_i => counter[1].ACLR
wb_rst_i => counter[0].ACLR
wb_rst_i => shift_out[6].ACLR
wb_rst_i => shift_out[5].ACLR
wb_rst_i => shift_out[4].ACLR
wb_rst_i => shift_out[3].ACLR
wb_rst_i => shift_out[2].ACLR
wb_rst_i => shift_out[1].ACLR
wb_rst_i => shift_out[0].ACLR
wb_rst_i => parity_xor.ACLR
wb_rst_i => bit_out.ACLR
wb_rst_i => tf_pop.ACLR
wb_rst_i => bit_counter[2].ACLR
wb_rst_i => bit_counter[1].ACLR
wb_rst_i => bit_counter[0].ACLR
wb_rst_i => aclr~0.IN0
lcr[0] => ~NO_FANOUT~
lcr[1] => ~NO_FANOUT~
lcr[2] => ~NO_FANOUT~
lcr[3] => tstate~6.DATAA
lcr[3] => tstate~5.DATAA
lcr[3] => tstate~4.DATAA
lcr[3] => bit_out~0.OUTPUTSELECT
lcr[4] => Mux0.IN4
lcr[5] => Mux0.IN3
lcr[6] => stx_pad_o~0.OUTPUTSELECT
lcr[7] => ~NO_FANOUT~
tf_push => tf_push~0.IN1
wb_dat_i[0] => tf_data_in[0].IN1
wb_dat_i[1] => tf_data_in[1].IN1
wb_dat_i[2] => tf_data_in[2].IN1
wb_dat_i[3] => tf_data_in[3].IN1
wb_dat_i[4] => tf_data_in[4].IN1
wb_dat_i[5] => tf_data_in[5].IN1
wb_dat_i[6] => tf_data_in[6].IN1
wb_dat_i[7] => tf_data_in[7].IN1
enable => tf_pop~1.OUTPUTSELECT
enable => bit_counter[0].ENA
enable => tstate[2]~reg0.ENA
enable => tstate[1]~reg0.ENA
enable => tstate[0]~reg0.ENA
enable => stx_o_tmp.ENA
enable => counter[4].ENA
enable => counter[3].ENA
enable => counter[2].ENA
enable => counter[1].ENA
enable => counter[0].ENA
enable => shift_out[6].ENA
enable => shift_out[5].ENA
enable => shift_out[4].ENA
enable => shift_out[3].ENA
enable => shift_out[2].ENA
enable => shift_out[1].ENA
enable => shift_out[0].ENA
enable => parity_xor.ENA
enable => bit_out.ENA
enable => bit_counter[2].ENA
enable => bit_counter[1].ENA
stx_pad_o <= stx_pad_o~0.DB_MAX_OUTPUT_PORT_TYPE
tstate[0] <= tstate[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tstate[1] <= tstate[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tstate[2] <= tstate[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tf_count[0] <= myfifo_8:myfifo_u1.usedw
tf_count[1] <= myfifo_8:myfifo_u1.usedw
tf_count[2] <= myfifo_8:myfifo_u1.usedw
tf_count[3] <= myfifo_8:myfifo_u1.usedw
tx_reset => aclr~0.IN1
lsr_mask => ~NO_FANOUT~


|uart_regs|uart_transmitter:transmitter|myfifo_8:myfifo_u1
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
wrreq => wrreq~0.IN1
rdreq => rdreq~0.IN1
clock => clock~0.IN1
aclr => aclr~0.IN1
q[0] <= scfifo:scfifo_component.q
q[1] <= scfifo:scfifo_component.q
q[2] <= scfifo:scfifo_component.q
q[3] <= scfifo:scfifo_component.q
q[4] <= scfifo:scfifo_component.q
q[5] <= scfifo:scfifo_component.q
q[6] <= scfifo:scfifo_component.q
q[7] <= scfifo:scfifo_component.q
full <= scfifo:scfifo_component.full
empty <= scfifo:scfifo_component.empty
usedw[0] <= scfifo:scfifo_component.usedw
usedw[1] <= scfifo:scfifo_component.usedw
usedw[2] <= scfifo:scfifo_component.usedw
usedw[3] <= scfifo:scfifo_component.usedw


|uart_regs|uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component
data[0] => scfifo_eb81:auto_generated.data[0]
data[1] => scfifo_eb81:auto_generated.data[1]
data[2] => scfifo_eb81:auto_generated.data[2]
data[3] => scfifo_eb81:auto_generated.data[3]
data[4] => scfifo_eb81:auto_generated.data[4]
data[5] => scfifo_eb81:auto_generated.data[5]
data[6] => scfifo_eb81:auto_generated.data[6]
data[7] => scfifo_eb81:auto_generated.data[7]
q[0] <= scfifo_eb81:auto_generated.q[0]
q[1] <= scfifo_eb81:auto_generated.q[1]
q[2] <= scfifo_eb81:auto_generated.q[2]
q[3] <= scfifo_eb81:auto_generated.q[3]
q[4] <= scfifo_eb81:auto_generated.q[4]
q[5] <= scfifo_eb81:auto_generated.q[5]
q[6] <= scfifo_eb81:auto_generated.q[6]
q[7] <= scfifo_eb81:auto_generated.q[7]
wrreq => scfifo_eb81:auto_generated.wrreq
rdreq => scfifo_eb81:auto_generated.rdreq
clock => scfifo_eb81:auto_generated.clock
aclr => scfifo_eb81:auto_generated.aclr
sclr => ~NO_FANOUT~
empty <= scfifo_eb81:auto_generated.empty
full <= scfifo_eb81:auto_generated.full
almost_full <= <GND>
almost_empty <= <GND>
usedw[0] <= scfifo_eb81:auto_generated.usedw[0]
usedw[1] <= scfifo_eb81:auto_generated.usedw[1]
usedw[2] <= scfifo_eb81:auto_generated.usedw[2]
usedw[3] <= scfifo_eb81:auto_generated.usedw[3]


|uart_regs|uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated
aclr => a_dpfifo_lh81:dpfifo.aclr
clock => a_dpfifo_lh81:dpfifo.clock
data[0] => a_dpfifo_lh81:dpfifo.data[0]
data[1] => a_dpfifo_lh81:dpfifo.data[1]
data[2] => a_dpfifo_lh81:dpfifo.data[2]
data[3] => a_dpfifo_lh81:dpfifo.data[3]
data[4] => a_dpfifo_lh81:dpfifo.data[4]
data[5] => a_dpfifo_lh81:dpfifo.data[5]
data[6] => a_dpfifo_lh81:dpfifo.data[6]
data[7] => a_dpfifo_lh81:dpfifo.data[7]
empty <= a_dpfifo_lh81:dpfifo.empty
full <= a_dpfifo_lh81:dpfifo.full
q[0] <= a_dpfifo_lh81:dpfifo.q[0]
q[1] <= a_dpfifo_lh81:dpfifo.q[1]
q[2] <= a_dpfifo_lh81:dpfifo.q[2]
q[3] <= a_dpfifo_lh81:dpfifo.q[3]
q[4] <= a_dpfifo_lh81:dpfifo.q[4]
q[5] <= a_dpfifo_lh81:dpfifo.q[5]
q[6] <= a_dpfifo_lh81:dpfifo.q[6]
q[7] <= a_dpfifo_lh81:dpfifo.q[7]
rdreq => a_dpfifo_lh81:dpfifo.rreq
usedw[0] <= a_dpfifo_lh81:dpfifo.usedw[0]
usedw[1] <= a_dpfifo_lh81:dpfifo.usedw[1]
usedw[2] <= a_dpfifo_lh81:dpfifo.usedw[2]
usedw[3] <= a_dpfifo_lh81:dpfifo.usedw[3]
wrreq => a_dpfifo_lh81:dpfifo.wreq


|uart_regs|uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo
aclr => a_fefifo_66f:fifo_state.aclr
aclr => cntr_tcb:rd_ptr_count.aclr
aclr => cntr_tcb:wr_ptr.aclr
clock => a_fefifo_66f:fifo_state.clock
clock => dpram_pf51:FIFOram.inclock
clock => dpram_pf51:FIFOram.outclock
clock => cntr_tcb:rd_ptr_count.clock
clock => cntr_tcb:wr_ptr.clock
data[0] => dpram_pf51:FIFOram.data[0]
data[1] => dpram_pf51:FIFOram.data[1]
data[2] => dpram_pf51:FIFOram.data[2]
data[3] => dpram_pf51:FIFOram.data[3]
data[4] => dpram_pf51:FIFOram.data[4]
data[5] => dpram_pf51:FIFOram.data[5]
data[6] => dpram_pf51:FIFOram.data[6]
data[7] => dpram_pf51:FIFOram.data[7]
empty <= a_fefifo_66f:fifo_state.empty
full <= a_fefifo_66f:fifo_state.full
q[0] <= dpram_pf51:FIFOram.q[0]
q[1] <= dpram_pf51:FIFOram.q[1]
q[2] <= dpram_pf51:FIFOram.q[2]
q[3] <= dpram_pf51:FIFOram.q[3]
q[4] <= dpram_pf51:FIFOram.q[4]
q[5] <= dpram_pf51:FIFOram.q[5]
q[6] <= dpram_pf51:FIFOram.q[6]
q[7] <= dpram_pf51:FIFOram.q[7]
rreq => a_fefifo_66f:fifo_state.rreq
rreq => valid_rreq.IN0
sclr => a_fefifo_66f:fifo_state.sclr
sclr => cntr_tcb:rd_ptr_count.sclr
sclr => cntr_tcb:wr_ptr.sclr
usedw[0] <= a_fefifo_66f:fifo_state.usedw_out[0]
usedw[1] <= a_fefifo_66f:fifo_state.usedw_out[1]
usedw[2] <= a_fefifo_66f:fifo_state.usedw_out[2]
usedw[3] <= a_fefifo_66f:fifo_state.usedw_out[3]
wreq => a_fefifo_66f:fifo_state.wreq
wreq => valid_wreq.IN0


|uart_regs|uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|a_fefifo_66f:fifo_state
aclr => cntr_9d7:count_usedw.aclr
clock => cntr_9d7:count_usedw.clock
clock => b_full.CLK
clock => b_non_empty.CLK
full <= b_full.DB_MAX_OUTPUT_PORT_TYPE
rreq => valid_rreq.IN0
sclr => cntr_9d7:count_usedw.sclr
usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[3] <= usedw[3].DB_MAX_OUTPUT_PORT_TYPE
wreq => valid_wreq.IN0


|uart_regs|uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|a_fefifo_66f:fifo_state|cntr_9d7:count_usedw
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
sclr => counter_cella0.SCLR
sclr => counter_cella1.SCLR
sclr => counter_cella2.SCLR
sclr => counter_cella3.SCLR
updown => counter_cella0.DATAB
updown => counter_cella1.DATAB
updown => counter_cella2.DATAB
updown => counter_cella3.DATAB


|uart_regs|uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|dpram_pf51:FIFOram
data[0] => altsyncram_gml1:altsyncram1.data_a[0]
data[1] => altsyncram_gml1:altsyncram1.data_a[1]
data[2] => altsyncram_gml1:altsyncram1.data_a[2]
data[3] => altsyncram_gml1:altsyncram1.data_a[3]
data[4] => altsyncram_gml1:altsyncram1.data_a[4]
data[5] => altsyncram_gml1:altsyncram1.data_a[5]