--a_fefifo ALLOW_RWCYCLE_WHEN_FULL=OFF LPM_NUMWORDS=16 lpm_widthad=4 OVERFLOW_CHECKING=ON UNDERFLOW_CHECKING=ON aclr clock empty full rreq sclr usedw_out wreq
--VERSION_BEGIN 4.0 cbx_fifo_common 2003:08:19:18:07:00:SJ cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_lpm_counter 2003:12:16:17:25:44:SJ cbx_lpm_decode 2003:03:25:17:43:04:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_stratixii 2003:11:06:16:12:54:SJ  VERSION_END


--  Copyright (C) 1988-2004 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
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--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
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FUNCTION lpm_counter (aclr, aload, aset, cin, clk_en, clock, cnt_en, data[LPM_WIDTH-1..0], sclr, sload, sset, updown)
WITH ( 	lpm_avalue,	lpm_direction,	lpm_modulus,	lpm_svalue,	lpm_width) 
RETURNS ( cout, eq[15..0], q[LPM_WIDTH-1..0]);

--synthesis_resources = lpm_counter 1 lut 2 
SUBDESIGN a_fefifo_qve
( 
	aclr	:	input;
	clock	:	input;
	empty	:	output;
	full	:	output;
	rreq	:	input;
	sclr	:	input;
	usedw_out[3..0]	:	output;
	wreq	:	input;
) 
VARIABLE 
	b_full : dffe;
	b_non_empty : dffe;
	count_usedw : lpm_counter
		WITH (
			lpm_width = 4
		);
	equal_af1[3..0]	: WIRE;
	equal_one[3..0]	: WIRE;
	is_almost_empty0	: WIRE;
	is_almost_empty1	: WIRE;
	is_almost_empty2	: WIRE;
	is_almost_empty3	: WIRE;
	is_almost_full0	: WIRE;
	is_almost_full1	: WIRE;
	is_almost_full2	: WIRE;
	is_almost_full3	: WIRE;
	usedw[3..0]	: WIRE;
	valid_rreq	: WIRE;
	valid_wreq	: WIRE;

BEGIN 
	b_full.CLK = clock;
	b_full.CLRN = (! aclr);
	b_full.D = ((b_full.Q & (b_full.Q $ (sclr # rreq))) # (((! b_full.Q) & b_non_empty.Q) & ((! sclr) & ((is_almost_full3 & wreq) & (! rreq)))));
	b_non_empty.CLK = clock;
	b_non_empty.CLRN = (! aclr);
	b_non_empty.D = (((b_full.Q & (b_full.Q $ sclr)) # (((! b_non_empty.Q) & wreq) & (! sclr))) # (((! b_full.Q) & b_non_empty.Q) & (((! b_full.Q) & b_non_empty.Q) $ (sclr # ((is_almost_empty3 & rreq) & (! wreq))))));
	count_usedw.aclr = aclr;
	count_usedw.clock = clock;
	count_usedw.cnt_en = (valid_wreq $ valid_rreq);
	count_usedw.sclr = sclr;
	count_usedw.updown = valid_wreq;
	empty = (! b_non_empty.Q);
	equal_af1[] = ( B"0", B"0", B"0", B"0");
	equal_one[] = ( B"1", B"1", B"1", B"0");
	full = b_full.Q;
	is_almost_empty0 = (usedw[0..0] $ equal_one[0..0]);
	is_almost_empty1 = ((usedw[1..1] $ equal_one[1..1]) & is_almost_empty0);
	is_almost_empty2 = ((usedw[2..2] $ equal_one[2..2]) & is_almost_empty1);
	is_almost_empty3 = ((usedw[3..3] $ equal_one[3..3]) & is_almost_empty2);
	is_almost_full0 = (usedw[0..0] $ equal_af1[0..0]);
	is_almost_full1 = ((usedw[1..1] $ equal_af1[1..1]) & is_almost_full0);
	is_almost_full2 = ((usedw[2..2] $ equal_af1[2..2]) & is_almost_full1);
	is_almost_full3 = ((usedw[3..3] $ equal_af1[3..3]) & is_almost_full2);
	usedw[] = count_usedw.q[];
	usedw_out[] = usedw[];
	valid_rreq = (rreq & b_non_empty.Q);
	valid_wreq = (wreq & (! b_full.Q));
END;
--VALID FILE