--a_dpfifo ADD_RAM_OUTPUT_REGISTER="OFF" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Stratix" LPM_NUMWORDS=16 LPM_SHOWAHEAD="OFF" lpm_width=10 lpm_widthu=4 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" aclr clock data empty full q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=70 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Stratix" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO"
--VERSION_BEGIN 7.1 cbx_altdpram 2007:03:30:09:43:02:SJ cbx_altsyncram 2007:03:22:08:29:24:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_fifo_common 2006:03:14:11:59:42:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_counter 2007:03:22:23:17:10:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_lpm_mux 2006:11:21:10:27:10:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_scfifo 2006:10:14:23:20:56:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_stratixiii 2007:03:13:14:47:12:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION a_fefifo_66f (aclr, clock, rreq, sclr, wreq)
RETURNS ( empty, full, usedw_out[3..0]);
FUNCTION dpram_2h51 (data[9..0], inclock, outclock, outclocken, rdaddress[3..0], wraddress[3..0], wren)
RETURNS ( q[9..0]);
FUNCTION cntr_tcb (aclr, clock, cnt_en, sclr)
RETURNS ( q[3..0]);

--synthesis_resources = ram_bits (AUTO) 160 
SUBDESIGN a_dpfifo_ui81
( 
	aclr	:	input;
	clock	:	input;
	data[9..0]	:	input;
	empty	:	output;
	full	:	output;
	q[9..0]	:	output;
	rreq	:	input;
	sclr	:	input;
	usedw[3..0]	:	output;
	wreq	:	input;
) 
VARIABLE 
	fifo_state : a_fefifo_66f;
	FIFOram : dpram_2h51;
	rd_ptr_count : cntr_tcb;
	wr_ptr : cntr_tcb;
	rd_ptr[3..0]	: WIRE;
	valid_rreq	: WIRE;
	valid_wreq	: WIRE;

BEGIN 
	fifo_state.aclr = aclr;
	fifo_state.clock = clock;
	fifo_state.rreq = rreq;
	fifo_state.sclr = sclr;
	fifo_state.wreq = wreq;
	FIFOram.data[] = data[];
	FIFOram.inclock = clock;
	FIFOram.outclock = clock;
	FIFOram.outclocken = (valid_rreq # sclr);
	FIFOram.rdaddress[] = ((! sclr) & rd_ptr[]);
	FIFOram.wraddress[] = wr_ptr.q[];
	FIFOram.wren = valid_wreq;
	rd_ptr_count.aclr = aclr;
	rd_ptr_count.clock = clock;
	rd_ptr_count.cnt_en = valid_rreq;
	rd_ptr_count.sclr = sclr;
	wr_ptr.aclr = aclr;
	wr_ptr.clock = clock;
	wr_ptr.cnt_en = valid_wreq;
	wr_ptr.sclr = sclr;
	empty = fifo_state.empty;
	full = fifo_state.full;
	q[] = FIFOram.q[];
	rd_ptr[] = rd_ptr_count.q[];
	usedw[] = fifo_state.usedw_out[];
	valid_rreq = (rreq & (! fifo_state.empty));
	valid_wreq = (wreq & (! fifo_state.full));
END;
--VALID FILE