--lpm_counter DEVICE_FAMILY="Stratix" lpm_width=4 aclr clock cnt_en q sclr updown
--VERSION_BEGIN 7.1 cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_counter 2007:03:22:23:17:10:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ  VERSION_END


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--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
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--  without limitation, that your use is for the sole purpose of 
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--  applicable agreement for further details.


FUNCTION stratix_lcell (aclr, aload, cin, clk, dataa, datab, datac, datad, ena, inverta, regcascin, sclr, sload)
WITH ( 	cin0_used,	cin1_used,	cin_used,	lut_mask,	operation_mode,	output_mode,	power_up,	register_cascade_mode,	sum_lutc_input,	synch_mode,	x_on_violation) 
RETURNS ( combout, cout, regout);

--synthesis_resources = lut 4 
SUBDESIGN cntr_9d7
( 
	aclr	:	input;
	clock	:	input;
	cnt_en	:	input;
	q[3..0]	:	output;
	sclr	:	input;
	updown	:	input;
) 
VARIABLE 
	counter_cella0 : stratix_lcell
		WITH (
			cin_used = "false",
			lut_mask = "5599",
			operation_mode = "arithmetic",
			synch_mode = "on"
		);
	counter_cella1 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella2 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella3 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "normal",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	aclr_actual	: WIRE;
	clk_en	: NODE;
	data[3..0]	: NODE;
	s_val[3..0]	: WIRE;
	safe_q[3..0]	: WIRE;
	sload	: NODE;
	sset	: NODE;
	updownDir	: WIRE;

BEGIN 
	counter_cella[3..0].aclr = aclr_actual;
	counter_cella[3..0].aload = B"0000";
	counter_cella[1].cin = counter_cella[0].cout;
	counter_cella[2].cin = counter_cella[1].cout;
	counter_cella[3].cin = counter_cella[2].cout;
	counter_cella[3..0].clk = clock;
	counter_cella[3..0].dataa = safe_q[];
	counter_cella[3..0].datab = updownDir;
	counter_cella[3..0].datac = ((sset & s_val[]) # ((! sset) & data[]));
	counter_cella[3].datad = B"1";
	counter_cella[3..0].ena = (clk_en & (((cnt_en # sclr) # sset) # sload));
	counter_cella[3..0].sclr = sclr;
	counter_cella[3..0].sload = (sset # sload);
	aclr_actual = aclr;
	clk_en = VCC;
	data[] = GND;
	q[] = safe_q[];
	s_val[] = B"1111";
	safe_q[] = counter_cella[3..0].regout;
	sload = GND;
	sset = GND;
	updownDir = updown;
END;
--VALID FILE