?? altsyncram_mmb1.tdf
字號(hào):
--altsyncram ADDRESS_ACLR_A=NONE ADDRESS_ACLR_B=NONE ADDRESS_REG_B=CLOCK1 DEVICE_FAMILY=Stratix INDATA_ACLR_A=NONE OPERATION_MODE=DUAL_PORT OUTDATA_ACLR_B=NONE OUTDATA_REG_B=UNREGISTERED RAM_BLOCK_TYPE=AUTO RDCONTROL_ACLR_B=NONE RDCONTROL_REG_B=CLOCK1 READ_DURING_WRITE_MODE_MIXED_PORTS=DONT_CARE WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=4 WIDTHAD_B=4 WRCONTROL_ACLR_A=NONE address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
--VERSION_BEGIN 4.0 cbx_altsyncram 2003:12:02:15:28:30:SJ cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_lpm_decode 2003:03:25:17:43:04:SJ cbx_lpm_mux 2003:10:21:14:09:22:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_stratix 2003:12:15:10:23:28:SJ cbx_stratixii 2003:11:06:16:12:54:SJ cbx_util 2003:12:05:10:31:30:SJ VERSION_END
-- Copyright (C) 1988-2004 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
FUNCTION stratix_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[15..0], portabyteenamasks[15..0], portadatain[143..0], portawe, portbaddr[15..0], portbbyteenamasks[15..0], portbdatain[143..0], portbrewe)
WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem1, mem2, mem3, mem4, mem5, mem6, mem7, mem8, mem9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH, PORT_A_BYTE_ENABLE_CLEAR, PORT_A_BYTE_ENABLE_MASK_WIDTH, PORT_A_DATA_IN_CLEAR, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_WRITE_ENABLE_CLEAR, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH, PORT_B_BYTE_ENABLE_CLEAR, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH, PORT_B_DATA_IN_CLEAR, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, RAM_BLOCK_TYPE)
RETURNS ( portadataout[143..0], portbdataout[143..0]);
--synthesis_resources = ram_bits (auto) 128
SUBDESIGN altsyncram_mmb1
(
address_a[3..0] : input;
address_b[3..0] : input;
clock0 : input;
clock1 : input;
clocken1 : input;
data_a[7..0] : input;
q_b[7..0] : output;
wren_a : input;
)
VARIABLE
ram_block2a0 : stratix_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 4,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 15,
PORT_A_LOGICAL_RAM_DEPTH = 16,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 4,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 15,
PORT_B_LOGICAL_RAM_DEPTH = 16,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a1 : stratix_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 4,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 15,
PORT_A_LOGICAL_RAM_DEPTH = 16,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 4,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 15,
PORT_B_LOGICAL_RAM_DEPTH = 16,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a2 : stratix_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 4,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 15,
PORT_A_LOGICAL_RAM_DEPTH = 16,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 4,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 15,
PORT_B_LOGICAL_RAM_DEPTH = 16,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a3 : stratix_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 4,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 15,
PORT_A_LOGICAL_RAM_DEPTH = 16,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 4,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 15,
PORT_B_LOGICAL_RAM_DEPTH = 16,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a4 : stratix_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 4,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 15,
PORT_A_LOGICAL_RAM_DEPTH = 16,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 4,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 15,
PORT_B_LOGICAL_RAM_DEPTH = 16,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a5 : stratix_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 4,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 15,
PORT_A_LOGICAL_RAM_DEPTH = 16,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 4,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 15,
PORT_B_LOGICAL_RAM_DEPTH = 16,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a6 : stratix_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 4,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 15,
PORT_A_LOGICAL_RAM_DEPTH = 16,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 4,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 15,
PORT_B_LOGICAL_RAM_DEPTH = 16,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a7 : stratix_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 4,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 15,
PORT_A_LOGICAL_RAM_DEPTH = 16,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 4,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 15,
PORT_B_LOGICAL_RAM_DEPTH = 16,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
address_a_wire[3..0] : WIRE;
address_b_wire[3..0] : WIRE;
BEGIN
ram_block2a[7..0].clk0 = clock0;
ram_block2a[7..0].clk1 = clock1;
ram_block2a[7..0].ena1 = clocken1;
ram_block2a[0].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
ram_block2a[1].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
ram_block2a[2].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
ram_block2a[3].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
ram_block2a[4].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
ram_block2a[5].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
ram_block2a[6].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
ram_block2a[7].portaaddr[] = ( B"000000000000", address_a_wire[3..0]);
ram_block2a[0].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[0..0]);
ram_block2a[1].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[1..1]);
ram_block2a[2].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[2..2]);
ram_block2a[3].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[3..3]);
ram_block2a[4].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[4..4]);
ram_block2a[5].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[5..5]);
ram_block2a[6].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[6..6]);
ram_block2a[7].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[7..7]);
ram_block2a[7..0].portawe = wren_a;
ram_block2a[0].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
ram_block2a[1].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
ram_block2a[2].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
ram_block2a[3].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
ram_block2a[4].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
ram_block2a[5].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
ram_block2a[6].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
ram_block2a[7].portbaddr[] = ( B"000000000000", address_b_wire[3..0]);
ram_block2a[0].portbrewe = B"1";
ram_block2a[1].portbrewe = B"1";
ram_block2a[2].portbrewe = B"1";
ram_block2a[3].portbrewe = B"1";
ram_block2a[4].portbrewe = B"1";
ram_block2a[5].portbrewe = B"1";
ram_block2a[6].portbrewe = B"1";
ram_block2a[7].portbrewe = B"1";
address_a_wire[] = address_a[];
address_b_wire[] = address_b[];
q_b[] = ( ram_block2a[7].portbdataout[0..0], ram_block2a[6].portbdataout[0..0], ram_block2a[5].portbdataout[0..0], ram_block2a[4].portbdataout[0..0], ram_block2a[3].portbdataout[0..0], ram_block2a[2].portbdataout[0..0], ram_block2a[1].portbdataout[0..0], ram_block2a[0].portbdataout[0..0]);
END;
--VALID FILE
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