{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 06 15:06:49 2008 " "Info: Processing started: Sat Dec 06 15:06:49 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uart_regs -c uart_regs " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart_regs -c uart_regs" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../core/myfifo_8.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../core/myfifo_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 myfifo_8 " "Info: Found entity 1: myfifo_8" {  } { { "../core/myfifo_8.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/core/myfifo_8.v" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../core/myfifo_10.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../core/myfifo_10.v" { { "Info" "ISGN_ENTITY_NAME" "1 myfifo_10 " "Info: Found entity 1: myfifo_10" {  } { { "../core/myfifo_10.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/core/myfifo_10.v" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/seriesPort.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../src/seriesPort.v" { { "Info" "ISGN_ENTITY_NAME" "1 series_port " "Info: Found entity 1: series_port" {  } { { "../src/seriesPort.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/seriesPort.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/uart_defines.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file ../src/uart_defines.v" {  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/uart_receiver.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../src/uart_receiver.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_receiver " "Info: Found entity 1: uart_receiver" {  } { { "../src/uart_receiver.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_receiver.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "rf_overrun uart_regs.v(115) " "Warning (10236): Verilog HDL Implicit Net warning at uart_regs.v(115): created implicit net for \"rf_overrun\"" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 115 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/uart_regs.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../src/uart_regs.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_regs " "Info: Found entity 1: uart_regs" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/uart_transmitter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../src/uart_transmitter.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_transmitter " "Info: Found entity 1: uart_transmitter" {  } { { "../src/uart_transmitter.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_transmitter.v" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "uart_regs " "Info: Elaborating entity \"uart_regs\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_regs.v(319) " "Warning (10230): Verilog HDL assignment warning at uart_regs.v(319): truncated value with size 32 to match size of target (1)" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 319 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_regs.v(328) " "Warning (10230): Verilog HDL assignment warning at uart_regs.v(328): truncated value with size 32 to match size of target (1)" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 328 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_regs.v(337) " "Warning (10230): Verilog HDL assignment warning at uart_regs.v(337): truncated value with size 32 to match size of target (1)" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 337 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_regs.v(346) " "Warning (10230): Verilog HDL assignment warning at uart_regs.v(346): truncated value with size 32 to match size of target (1)" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 346 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_regs.v(355) " "Warning (10230): Verilog HDL assignment warning at uart_regs.v(355): truncated value with size 32 to match size of target (1)" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 355 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_regs.v(364) " "Warning (10230): Verilog HDL assignment warning at uart_regs.v(364): truncated value with size 32 to match size of target (1)" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 364 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 uart_regs.v(373) " "Warning (10230): Verilog HDL assignment warning at uart_regs.v(373): truncated value with size 32 to match size of target (16)" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 373 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 uart_regs.v(375) " "Warning (10230): Verilog HDL assignment warning at uart_regs.v(375): truncated value with size 32 to match size of target (16)" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 375 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 uart_regs.v(400) " "Warning (10230): Verilog HDL assignment warning at uart_regs.v(400): truncated value with size 32 to match size of target (8)" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 400 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_regs.v(455) " "Warning (10230): Verilog HDL assignment warning at uart_regs.v(455): truncated value with size 32 to match size of target (1)" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 455 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_regs.v(462) " "Warning (10230): Verilog HDL assignment warning at uart_regs.v(462): truncated value with size 32 to match size of target (1)" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 462 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}