{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rbit_in uart_receiver.v(38) " "Warning (10036): Verilog HDL or VHDL warning at uart_receiver.v(38): object \"rbit_in\" assigned a value but never read" {  } { { "../src/uart_receiver.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_receiver.v" 38 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rcounter16_eq_1 uart_receiver.v(72) " "Warning (10036): Verilog HDL or VHDL warning at uart_receiver.v(72): object \"rcounter16_eq_1\" assigned a value but never read" {  } { { "../src/uart_receiver.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_receiver.v" 72 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_receiver.v(70) " "Warning (10230): Verilog HDL assignment warning at uart_receiver.v(70): truncated value with size 32 to match size of target (1)" {  } { { "../src/uart_receiver.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_receiver.v" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_receiver.v(71) " "Warning (10230): Verilog HDL assignment warning at uart_receiver.v(71): truncated value with size 32 to match size of target (1)" {  } { { "../src/uart_receiver.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_receiver.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_receiver.v(72) " "Warning (10230): Verilog HDL assignment warning at uart_receiver.v(72): truncated value with size 32 to match size of target (1)" {  } { { "../src/uart_receiver.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_receiver.v" 72 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 uart_receiver.v(206) " "Warning (10230): Verilog HDL assignment warning at uart_receiver.v(206): truncated value with size 32 to match size of target (8)" {  } { { "../src/uart_receiver.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_receiver.v" 206 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 uart_receiver.v(221) " "Warning (10230): Verilog HDL assignment warning at uart_receiver.v(221): truncated value with size 32 to match size of target (10)" {  } { { "../src/uart_receiver.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_receiver.v" 221 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "myfifo_10 uart_receiver:receiver\|myfifo_10:myfifo_u " "Info: Elaborating entity \"myfifo_10\" for hierarchy \"uart_receiver:receiver\|myfifo_10:myfifo_u\"" {  } { { "../src/uart_receiver.v" "myfifo_u" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_receiver.v" 66 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component " "Info: Elaborating entity \"scfifo\" for hierarchy \"uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\"" {  } { { "../core/myfifo_10.v" "scfifo_component" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/core/myfifo_10.v" 89 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component " "Info: Elaborated megafunction instantiation \"uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\"" {  } { { "../core/myfifo_10.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/core/myfifo_10.v" 89 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_nc81.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/scfifo_nc81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_nc81 " "Info: Found entity 1: scfifo_nc81" {  } { { "db/scfifo_nc81.tdf" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/scfifo_nc81.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_nc81 uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nc81:auto_generated " "Info: Elaborating entity \"scfifo_nc81\" for hierarchy \"uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nc81:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_ui81.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_ui81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_ui81 " "Info: Found entity 1: a_dpfifo_ui81" {  } { { "db/a_dpfifo_ui81.tdf" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/a_dpfifo_ui81.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_ui81 uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nc81:auto_generated\|a_dpfifo_ui81:dpfifo " "Info: Elaborating entity \"a_dpfifo_ui81\" for hierarchy \"uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nc81:auto_generated\|a_dpfifo_ui81:dpfifo\"" {  } { { "db/scfifo_nc81.tdf" "dpfifo" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/scfifo_nc81.tdf" 37 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_2h51.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dpram_2h51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_2h51 " "Info: Found entity 1: dpram_2h51" {  } { { "db/dpram_2h51.tdf" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/dpram_2h51.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_2h51 uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nc81:auto_generated\|a_dpfifo_ui81:dpfifo\|dpram_2h51:FIFOram " "Info: Elaborating entity \"dpram_2h51\" for hierarchy \"uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nc81:auto_generated\|a_dpfifo_ui81:dpfifo\|dpram_2h51:FIFOram\"" {  } { { "db/a_dpfifo_ui81.tdf" "FIFOram" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/a_dpfifo_ui81.tdf" 43 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4pl1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4pl1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4pl1 " "Info: Found entity 1: altsyncram_4pl1" {  } { { "db/altsyncram_4pl1.tdf" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/altsyncram_4pl1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4pl1 uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nc81:auto_generated\|a_dpfifo_ui81:dpfifo\|dpram_2h51:FIFOram\|altsyncram_4pl1:altsyncram1 " "Info: Elaborating entity \"altsyncram_4pl1\" for hierarchy \"uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nc81:auto_generated\|a_dpfifo_ui81:dpfifo\|dpram_2h51:FIFOram\|altsyncram_4pl1:altsyncram1\"" {  } { { "db/dpram_2h51.tdf" "altsyncram1" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/dpram_2h51.tdf" 36 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 501 -1 0 } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 180 -1 0 } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 180 -1 0 } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 346 -1 0 } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 355 -1 0 } } { "../src/uart_transmitter.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_transmitter.v" 27 -1 0 } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 206 -1 0 } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 206 -1 0 } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 301 -1 0 } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 301 -1 0 } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 97 -1 0 } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v" 97 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "437 " "Info: Implemented 437 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "392 " "Info: Implemented 392 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_RAMS" "18 " "Info: Implemented 18 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/uart_regs.map.smsg " "Info: Generated suppressed messages file E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/uart_regs.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 21 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 21 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "143 " "Info: Allocated 143 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 06 15:06:59 2008 " "Info: Processing ended: Sat Dec 06 15:06:59 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}