?? uart_regs.map.rpt
字號:
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Use smart compilation ; Off ; Off ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------+
; ../core/myfifo_8.v ; yes ; User Verilog HDL File ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/core/myfifo_8.v ;
; ../core/myfifo_10.v ; yes ; User Verilog HDL File ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/core/myfifo_10.v ;
; ../src/uart_defines.v ; yes ; User Verilog HDL File ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_defines.v ;
; ../src/uart_receiver.v ; yes ; User Verilog HDL File ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_receiver.v ;
; ../src/uart_regs.v ; yes ; User Verilog HDL File ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_regs.v ;
; ../src/uart_transmitter.v ; yes ; User Verilog HDL File ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/src/uart_transmitter.v ;
; scfifo.tdf ; yes ; Megafunction ; d:/program files/quartus7.1/quartus/libraries/megafunctions/scfifo.tdf ;
; a_regfifo.inc ; yes ; Megafunction ; d:/program files/quartus7.1/quartus/libraries/megafunctions/a_regfifo.inc ;
; a_dpfifo.inc ; yes ; Megafunction ; d:/program files/quartus7.1/quartus/libraries/megafunctions/a_dpfifo.inc ;
; a_i2fifo.inc ; yes ; Megafunction ; d:/program files/quartus7.1/quartus/libraries/megafunctions/a_i2fifo.inc ;
; a_fffifo.inc ; yes ; Megafunction ; d:/program files/quartus7.1/quartus/libraries/megafunctions/a_fffifo.inc ;
; a_f2fifo.inc ; yes ; Megafunction ; d:/program files/quartus7.1/quartus/libraries/megafunctions/a_f2fifo.inc ;
; aglobal71.inc ; yes ; Megafunction ; d:/program files/quartus7.1/quartus/libraries/megafunctions/aglobal71.inc ;
; db/scfifo_eb81.tdf ; yes ; Auto-Generated Megafunction ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/scfifo_eb81.tdf ;
; db/a_dpfifo_lh81.tdf ; yes ; Auto-Generated Megafunction ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/a_dpfifo_lh81.tdf ;
; db/a_fefifo_66f.tdf ; yes ; Auto-Generated Megafunction ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/a_fefifo_66f.tdf ;
; db/cntr_9d7.tdf ; yes ; Auto-Generated Megafunction ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/cntr_9d7.tdf ;
; db/dpram_pf51.tdf ; yes ; Auto-Generated Megafunction ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/dpram_pf51.tdf ;
; db/altsyncram_gml1.tdf ; yes ; Auto-Generated Megafunction ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/altsyncram_gml1.tdf ;
; db/cntr_tcb.tdf ; yes ; Auto-Generated Megafunction ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/cntr_tcb.tdf ;
; db/scfifo_nc81.tdf ; yes ; Auto-Generated Megafunction ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/scfifo_nc81.tdf ;
; db/a_dpfifo_ui81.tdf ; yes ; Auto-Generated Megafunction ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/a_dpfifo_ui81.tdf ;
; db/dpram_2h51.tdf ; yes ; Auto-Generated Megafunction ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/dpram_2h51.tdf ;
; db/altsyncram_4pl1.tdf ; yes ; Auto-Generated Megafunction ; E:/My design/Altera設計文檔/Example-b3-1/uart_regs/dev/db/altsyncram_4pl1.tdf ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 392 ;
; -- Combinational with no register ; 194 ;
; -- Register only ; 48 ;
; -- Combinational with a register ; 150 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 172 ;
; -- 3 input functions ; 71 ;
; -- 2 input functions ; 86 ;
; -- 1 input functions ; 14 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 332 ;
; -- arithmetic mode ; 60 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 31 ;
; -- asynchronous clear/load mode ; 198 ;
; ; ;
; Total registers ; 198 ;
; Total logic cells in carry chains ; 71 ;
; I/O pins ; 27 ;
; Total memory bits ; 288 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 175 ;
; Total fan-out ; 1907 ;
; Average fan-out ; 4.36 ;
+---------------------------------------------+-------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |uart_regs ; 392 (210) ; 198 ; 288 ; 0 ; 0 ; 0 ; 0 ; 27 ; 0 ; 194 (111) ; 48 (46) ; 150 (53) ; 71 (24) ; 0 (0) ; |uart_regs ; work ;
; |uart_receiver:receiver| ; 102 (80) ; 63 ; 160 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 39 (31) ; 1 (1) ; 62 (48) ; 30 (18) ; 0 (0) ; |uart_regs|uart_receiver:receiver ; work ;
; |myfifo_10:myfifo_u| ; 22 (0) ; 14 ; 160 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 14 (0) ; 12 (0) ; 0 (0) ; |uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u ; work ;
; |scfifo:scfifo_component| ; 22 (0) ; 14 ; 160 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 14 (0) ; 12 (0) ; 0 (0) ; |uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component ; work ;
; |scfifo_nc81:auto_generated| ; 22 (0) ; 14 ; 160 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 14 (0) ; 12 (0) ; 0 (0) ; |uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated ; work ;
; |a_dpfifo_ui81:dpfifo| ; 22 (3) ; 14 ; 160 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (3) ; 0 (0) ; 14 (0) ; 12 (0) ; 0 (0) ; |uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo ; work ;
; |a_fefifo_66f:fifo_state| ; 11 (6) ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (4) ; 0 (0) ; 6 (2) ; 4 (0) ; 0 (0) ; |uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|a_fefifo_66f:fifo_state ; work ;
; |cntr_9d7:count_usedw| ; 5 (5) ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; 4 (4) ; 0 (0) ; |uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|a_fefifo_66f:fifo_state|cntr_9d7:count_usedw ; work ;
; |cntr_tcb:rd_ptr_count| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; 0 (0) ; |uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|cntr_tcb:rd_ptr_count ; work ;
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