E2_safe_q[2] = DFFEA(E2_safe_q[2]_lut_out, clk, !C1L93, , K1L1, , );

--E2L7 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[2]~COUT
--operation mode is arithmetic

E2L7 = CARRY(!E2L5 & (E2_safe_q[2] $ !J1L2));


--E2_safe_q[1] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[1]
--operation mode is arithmetic

E2_safe_q[1]_carry_eqn = E2L3;
E2_safe_q[1]_lut_out = E2_safe_q[1] $ E2_safe_q[1]_carry_eqn;
E2_safe_q[1] = DFFEA(E2_safe_q[1]_lut_out, clk, !C1L93, , K1L1, , );

--E2L5 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[1]~COUT
--operation mode is arithmetic

E2L5 = CARRY(E2_safe_q[1] $ J1L2 # !E2L3);


--E2_safe_q[0] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[0]
--operation mode is arithmetic

E2_safe_q[0]_lut_out = !E2_safe_q[0];
E2_safe_q[0] = DFFEA(E2_safe_q[0]_lut_out, clk, !C1L93, , K1L1, , );

--E2L3 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[0]~COUT
--operation mode is arithmetic

E2L3 = CARRY(E2_safe_q[0] $ !J1L2);


--E7_safe_q[3] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[3]
--operation mode is normal

E7_safe_q[3]_carry_eqn = E7L7;
E7_safe_q[3]_lut_out = E7_safe_q[3] $ (K2L9 & E7_safe_q[3]_carry_eqn);
E7_safe_q[3] = DFFEA(E7_safe_q[3]_lut_out, clk, !D1_i12, , , , );


--E7_safe_q[2] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[2]
--operation mode is arithmetic

E7_safe_q[2]_carry_eqn = E7L5;
E7_safe_q[2]_lut_out = E7_safe_q[2] $ (K2L9 & !E7_safe_q[2]_carry_eqn);
E7_safe_q[2] = DFFEA(E7_safe_q[2]_lut_out, clk, !D1_i12, , , , );

--E7L7 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|counter_cell[2]~COUT
--operation mode is arithmetic

E7L7 = CARRY(E7_safe_q[2] & !E7L5);


--E7_safe_q[1] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[1]
--operation mode is arithmetic

E7_safe_q[1]_carry_eqn = E7L3;
E7_safe_q[1]_lut_out = E7_safe_q[1] $ (K2L9 & E7_safe_q[1]_carry_eqn);
E7_safe_q[1] = DFFEA(E7_safe_q[1]_lut_out, clk, !D1_i12, , , , );

--E7L5 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|counter_cell[1]~COUT
--operation mode is arithmetic

E7L5 = CARRY(!E7L3 # !E7_safe_q[1]);


--E7_safe_q[0] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[0]
--operation mode is arithmetic

E7_safe_q[0]_lut_out = E7_safe_q[0] $ K2L9;
E7_safe_q[0] = DFFEA(E7_safe_q[0]_lut_out, clk, !D1_i12, , , , );

--E7L3 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|counter_cell[0]~COUT
--operation mode is arithmetic

E7L3 = CARRY(E7_safe_q[0]);


--E6_safe_q[3] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[3]
--operation mode is normal

E6_safe_q[3]_carry_eqn = E6L7;
E6_safe_q[3]_lut_out = E6_safe_q[3] $ (K2_valid_rreq & E6_safe_q[3]_carry_eqn);
E6_safe_q[3] = DFFEA(E6_safe_q[3]_lut_out, clk, !D1_i12, , , , );


--E6_safe_q[2] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[2]
--operation mode is arithmetic

E6_safe_q[2]_carry_eqn = E6L5;
E6_safe_q[2]_lut_out = E6_safe_q[2] $ (K2_valid_rreq & !E6_safe_q[2]_carry_eqn);
E6_safe_q[2] = DFFEA(E6_safe_q[2]_lut_out, clk, !D1_i12, , , , );

--E6L7 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|counter_cell[2]~COUT
--operation mode is arithmetic

E6L7 = CARRY(E6_safe_q[2] & !E6L5);


--E6_safe_q[1] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[1]
--operation mode is arithmetic

E6_safe_q[1]_carry_eqn = E6L3;
E6_safe_q[1]_lut_out = E6_safe_q[1] $ (K2_valid_rreq & E6_safe_q[1]_carry_eqn);
E6_safe_q[1] = DFFEA(E6_safe_q[1]_lut_out, clk, !D1_i12, , , , );

--E6L5 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|counter_cell[1]~COUT
--operation mode is arithmetic

E6L5 = CARRY(!E6L3 # !E6_safe_q[1]);


--E6_safe_q[0] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[0]
--operation mode is arithmetic

E6_safe_q[0]_lut_out = E6_safe_q[0] $ K2_valid_rreq;
E6_safe_q[0] = DFFEA(E6_safe_q[0]_lut_out, clk, !D1_i12, , , , );

--E6L3 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|counter_cell[0]~COUT
--operation mode is arithmetic

E6L3 = CARRY(E6_safe_q[0]);


--S1_q_b[0] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[0]
S1_q_b[0]_PORT_A_data_in = wb_dat_i[0];
S1_q_b[0]_PORT_A_data_in_reg = DFFE(S1_q_b[0]_PORT_A_data_in, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[0]_PORT_A_address_reg = DFFE(S1_q_b[0]_PORT_A_address, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[0]_PORT_B_address_reg = DFFE(S1_q_b[0]_PORT_B_address, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_PORT_A_write_enable = K2L9;
S1_q_b[0]_PORT_A_write_enable_reg = DFFE(S1_q_b[0]_PORT_A_write_enable, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_read_enable = VCC;
S1_q_b[0]_PORT_B_read_enable_reg = DFFE(S1_q_b[0]_PORT_B_read_enable, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_clock_0 = clk;
S1_q_b[0]_clock_1 = clk;
S1_q_b[0]_clock_enable_1 = K2_valid_rreq;
S1_q_b[0]_PORT_B_data_out = MEMORY(S1_q_b[0]_PORT_A_data_in_reg, , S1_q_b[0]_PORT_A_address_reg, S1_q_b[0]_PORT_B_address_reg, S1_q_b[0]_PORT_A_write_enable_reg, S1_q_b[0]_PORT_B_read_enable_reg, , , S1_q_b[0]_clock_0, S1_q_b[0]_clock_1, , S1_q_b[0]_clock_enable_1, , );
S1_q_b[0] = S1_q_b[0]_PORT_B_data_out[0];


--S1_q_b[1] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[1]
S1_q_b[1]_PORT_A_data_in = wb_dat_i[1];
S1_q_b[1]_PORT_A_data_in_reg = DFFE(S1_q_b[1]_PORT_A_data_in, S1_q_b[1]_clock_0, , , );
S1_q_b[1]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[1]_PORT_A_address_reg = DFFE(S1_q_b[1]_PORT_A_address, S1_q_b[1]_clock_0, , , );
S1_q_b[1]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[1]_PORT_B_address_reg = DFFE(S1_q_b[1]_PORT_B_address, S1_q_b[1]_clock_1, , , S1_q_b[1]_clock_enable_1);
S1_q_b[1]_PORT_A_write_enable = K2L9;
S1_q_b[1]_PORT_A_write_enable_reg = DFFE(S1_q_b[1]_PORT_A_write_enable, S1_q_b[1]_clock_0, , , );
S1_q_b[1]_PORT_B_read_enable = VCC;
S1_q_b[1]_PORT_B_read_enable_reg = DFFE(S1_q_b[1]_PORT_B_read_enable, S1_q_b[1]_clock_1, , , S1_q_b[1]_clock_enable_1);
S1_q_b[1]_clock_0 = clk;
S1_q_b[1]_clock_1 = clk;
S1_q_b[1]_clock_enable_1 = K2_valid_rreq;
S1_q_b[1]_PORT_B_data_out = MEMORY(S1_q_b[1]_PORT_A_data_in_reg, , S1_q_b[1]_PORT_A_address_reg, S1_q_b[1]_PORT_B_address_reg, S1_q_b[1]_PORT_A_write_enable_reg, S1_q_b[1]_PORT_B_read_enable_reg, , , S1_q_b[1]_clock_0, S1_q_b[1]_clock_1, , S1_q_b[1]_clock_enable_1, , );
S1_q_b[1] = S1_q_b[1]_PORT_B_data_out[0];


--S1_q_b[2] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[2]
S1_q_b[2]_PORT_A_data_in = wb_dat_i[2];
S1_q_b[2]_PORT_A_data_in_reg = DFFE(S1_q_b[2]_PORT_A_data_in, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[2]_PORT_A_address_reg = DFFE(S1_q_b[2]_PORT_A_address, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[2]_PORT_B_address_reg = DFFE(S1_q_b[2]_PORT_B_address, S1_q_b[2]_clock_1, , , S1_q_b[2]_clock_enable_1);
S1_q_b[2]_PORT_A_write_enable = K2L9;
S1_q_b[2]_PORT_A_write_enable_reg = DFFE(S1_q_b[2]_PORT_A_write_enable, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_read_enable = VCC;
S1_q_b[2]_PORT_B_read_enable_reg = DFFE(S1_q_b[2]_PORT_B_read_enable, S1_q_b[2]_clock_1, , , S1_q_b[2]_clock_enable_1);
S1_q_b[2]_clock_0 = clk;
S1_q_b[2]_clock_1 = clk;
S1_q_b[2]_clock_enable_1 = K2_valid_rreq;
S1_q_b[2]_PORT_B_data_out = MEMORY(S1_q_b[2]_PORT_A_data_in_reg, , S1_q_b[2]_PORT_A_address_reg, S1_q_b[2]_PORT_B_address_reg, S1_q_b[2]_PORT_A_write_enable_reg, S1_q_b[2]_PORT_B_read_enable_reg, , , S1_q_b[2]_clock_0, S1_q_b[2]_clock_1, , S1_q_b[2]_clock_enable_1, , );
S1_q_b[2] = S1_q_b[2]_PORT_B_data_out[0];


--S1_q_b[3] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[3]
S1_q_b[3]_PORT_A_data_in = wb_dat_i[3];
S1_q_b[3]_PORT_A_data_in_reg = DFFE(S1_q_b[3]_PORT_A_data_in, S1_q_b[3]_clock_0, , , );
S1_q_b[3]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[3]_PORT_A_address_reg = DFFE(S1_q_b[3]_PORT_A_address, S1_q_b[3]_clock_0, , , );
S1_q_b[3]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[3]_PORT_B_address_reg = DFFE(S1_q_b[3]_PORT_B_address, S1_q_b[3]_clock_1, , , S1_q_b[3]_clock_enable_1);
S1_q_b[3]_PORT_A_write_enable = K2L9;
S1_q_b[3]_PORT_A_write_enable_reg = DFFE(S1_q_b[3]_PORT_A_write_enable, S1_q_b[3]_clock_0, , , );
S1_q_b[3]_PORT_B_read_enable = VCC;
S1_q_b[3]_PORT_B_read_enable_reg = DFFE(S1_q_b[3]_PORT_B_read_enable, S1_q_b[3]_clock_1, , , S1_q_b[3]_clock_enable_1);
S1_q_b[3]_clock_0 = clk;
S1_q_b[3]_clock_1 = clk;
S1_q_b[3]_clock_enable_1 = K2_valid_rreq;
S1_q_b[3]_PORT_B_data_out = MEMORY(S1_q_b[3]_PORT_A_data_in_reg, , S1_q_b[3]_PORT_A_address_reg, S1_q_b[3]_PORT_B_address_reg, S1_q_b[3]_PORT_A_write_enable_reg, S1_q_b[3]_PORT_B_read_enable_reg, , , S1_q_b[3]_clock_0, S1_q_b[3]_clock_1, , S1_q_b[3]_clock_enable_1, , );
S1_q_b[3] = S1_q_b[3]_PORT_B_data_out[0];


--S1_q_b[4] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[4]
S1_q_b[4]_PORT_A_data_in = wb_dat_i[4];
S1_q_b[4]_PORT_A_data_in_reg = DFFE(S1_q_b[4]_PORT_A_data_in, S1_q_b[4]_clock_0, , , );
S1_q_b[4]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[4]_PORT_A_address_reg = DFFE(S1_q_b[4]_PORT_A_address, S1_q_b[4]_clock_0, , , );
S1_q_b[4]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[4]_PORT_B_address_reg = DFFE(S1_q_b[4]_PORT_B_address, S1_q_b[4]_clock_1, , , S1_q_b[4]_clock_enable_1);
S1_q_b[4]_PORT_A_write_enable = K2L9;
S1_q_b[4]_PORT_A_write_enable_reg = DFFE(S1_q_b[4]_PORT_A_write_enable, S1_q_b[4]_clock_0, , , );
S1_q_b[4]_PORT_B_read_enable = VCC;
S1_q_b[4]_PORT_B_read_enable_reg = DFFE(S1_q_b[4]_PORT_B_read_enable, S1_q_b[4]_clock_1, , , S1_q_b[4]_clock_enable_1);
S1_q_b[4]_clock_0 = clk;
S1_q_b[4]_clock_1 = clk;
S1_q_b[4]_clock_enable_1 = K2_valid_rreq;
S1_q_b[4]_PORT_B_data_out = MEMORY(S1_q_b[4]_PORT_A_data_in_reg, , S1_q_b[4]_PORT_A_address_reg, S1_q_b[4]_PORT_B_address_reg, S1_q_b[4]_PORT_A_write_enable_reg, S1_q_b[4]_PORT_B_read_enable_reg, , , S1_q_b[4]_clock_0, S1_q_b[4]_clock_1, , S1_q_b[4]_clock_enable_1, , );
S1_q_b[4] = S1_q_b[4]_PORT_B_data_out[0];


--S1_q_b[5] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[5]
S1_q_b[5]_PORT_A_data_in = wb_dat_i[5];
S1_q_b[5]_PORT_A_data_in_reg = DFFE(S1_q_b[5]_PORT_A_data_in, S1_q_b[5]_clock_0, , , );
S1_q_b[5]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[5]_PORT_A_address_reg = DFFE(S1_q_b[5]_PORT_A_address, S1_q_b[5]_clock_0, , , );
S1_q_b[5]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[5]_PORT_B_address_reg = DFFE(S1_q_b[5]_PORT_B_address, S1_q_b[5]_clock_1, , , S1_q_b[5]_clock_enable_1);
S1_q_b[5]_PORT_A_write_enable = K2L9;
S1_q_b[5]_PORT_A_write_enable_reg = DFFE(S1_q_b[5]_PORT_A_write_enable, S1_q_b[5]_clock_0, , , );
S1_q_b[5]_PORT_B_read_enable = VCC;
S1_q_b[5]_PORT_B_read_enable_reg = DFFE(S1_q_b[5]_PORT_B_read_enable, S1_q_b[5]_clock_1, , , S1_q_b[5]_clock_enable_1);
S1_q_b[5]_clock_0 = clk;
S1_q_b[5]_clock_1 = clk;
S1_q_b[5]_clock_enable_1 = K2_valid_rreq;
S1_q_b[5]_PORT_B_data_out = MEMORY(S1_q_b[5]_PORT_A_data_in_reg, , S1_q_b[5]_PORT_A_address_reg, S1_q_b[5]_PORT_B_address_reg, S1_q_b[5]_PORT_A_write_enable_reg, S1_q_b[5]_PORT_B_read_enable_reg, , , S1_q_b[5]_clock_0, S1_q_b[5]_clock_1, , S1_q_b[5]_clock_enable_1, , );
S1_q_b[5] = S1_q_b[5]_PORT_B_data_out[0];


--S1_q_b[6] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[6]
S1_q_b[6]_PORT_A_data_in = wb_dat_i[6];
S1_q_b[6]_PORT_A_data_in_reg = DFFE(S1_q_b[6]_PORT_A_data_in, S1_q_b[6]_clock_0, , , );
S1_q_b[6]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[6]_PORT_A_address_reg = DFFE(S1_q_b[6]_PORT_A_address, S1_q_b[6]_clock_0, , , );
S1_q_b[6]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[6]_PORT_B_address_reg = DFFE(S1_q_b[6]_PORT_B_address, S1_q_b[6]_clock_1, , , S1_q_b[6]_clock_enable_1);
S1_q_b[6]_PORT_A_write_enable = K2L9;
S1_q_b[6]_PORT_A_write_enable_reg = DFFE(S1_q_b[6]_PORT_A_write_enable, S1_q_b[6]_clock_0, , , );
S1_q_b[6]_PORT_B_read_enable = VCC;
S1_q_b[6]_PORT_B_read_enable_reg = DFFE(S1_q_b[6]_PORT_B_read_enable, S1_q_b[6]_clock_1, , , S1_q_b[6]_clock_enable_1);
S1_q_b[6]_clock_0 = clk;
S1_q_b[6]_clock_1 = clk;
S1_q_b[6]_clock_enable_1 = K2_valid_rreq;
S1_q_b[6]_PORT_B_data_out = MEMORY(S1_q_b[6]_PORT_A_data_in_reg, , S1_q_b[6]_PORT_A_address_reg, S1_q_b[6]_PORT_B_address_reg, S1_q_b[6]_PORT_A_write_enable_reg, S1_q_b[6]_PORT_B_read_enable_reg, , , S1_q_b[6]_clock_0, S1_q_b[6]_clock_1, , S1_q_b[6]_clock_enable_1, , );
S1_q_b[6] = S1_q_b[6]_PORT_B_data_out[0];


--S1_q_b[7] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[7]
S1_q_b[7]_PORT_A_data_in = wb_dat_i[7];
S1_q_b[7]_PORT_A_data_in_reg = DFFE(S1_q_b[7]_PORT_A_data_in, S1_q_b[7]_clock_0, , , );
S1_q_b[7]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[7]_PORT_A_address_reg = DFFE(S1_q_b[7]_PORT_A_address, S1_q_b[7]_clock_0, , , );
S1_q_b[7]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[7]_PORT_B_address_reg = DFFE(S1_q_b[7]_PORT_B_address, S1_q_b[7]_clock_1, , , S1_q_b[7]_clock_enable_1);
S1_q_b[7]_PORT_A_write_enable = K2L9;
S1_q_b[7]_PORT_A_write_enable_reg = DFFE(S1_q_b[7]_PORT_A_write_enable, S1_q_b[7]_clock_0, , , );
S1_q_b[7]_PORT_B_read_enable = VCC;
S1_q_b[7]_PORT_B_read_enable_reg = DFFE(S1_q_b[7]_PORT_B_read_enable, S1_q_b[7]_clock_1, , , S1_q_b[7]_clock_enable_1);
S1_q_b[7]_clock_0 = clk;
S1_q_b[7]_clock_1 = clk;
S1_q_b[7]_clock_enable_1 = K2_valid_rreq;
S1_q_b[7]_PORT_B_data_out = MEMORY(S1_q_b[7]_PORT_A_data_in_reg, , S1_q_b[7]_PORT_A_address_reg, S1_q_b[7]_PORT_B_address_reg, S1_q_b[7]_PORT_A_write_enable_reg, S1_q_b[7]_PORT_B_read_enable_reg, , , S1_q_b[7]_clock_0, S1_q_b[7]_clock_1, , S1_q_b[7]_clock_enable_1, , );
S1_q_b[7] = S1_q_b[7]_PORT_B_data_out[0];


--E5_safe_q[3] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[3]
--operation mode is normal

E5_safe_q[3]_carry_eqn = E5L7;
E5_safe_q[3]_lut_out = E5_safe_q[3] $ E5_safe_q[3]_carry_eqn;
E5_safe_q[3] = DFFEA(E5_safe_q[3]_lut_out, clk, !D1_i12, , K2L1, , );


--E5_safe_q[2] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[2]
--operation mode is arithmetic

E5_safe_q[2]_carry_eqn = E5L5;
E5_safe_q[2]_lut_out = E5_safe_q[2] $ !E5_safe_q[2]_carry_eqn;
E5_safe_q[2] = DFFEA(E5_safe_q[2]_lut_out, clk, !D1_i12, , K2L1, , );

--E5L7 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[2]~COUT