?? select_32.tan.rpt
字號:
Classic Timing Analyzer report for select_32
Sun Dec 07 11:49:28 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 10.200 ns ; S ; Y[0] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM3256ATI144-10 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+-------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+-------+-------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+-------+-------+
; N/A ; None ; 10.200 ns ; S ; Y[15] ;
; N/A ; None ; 10.200 ns ; S ; Y[14] ;
; N/A ; None ; 10.200 ns ; S ; Y[13] ;
; N/A ; None ; 10.200 ns ; S ; Y[12] ;
; N/A ; None ; 10.200 ns ; S ; Y[11] ;
; N/A ; None ; 10.200 ns ; S ; Y[10] ;
; N/A ; None ; 10.200 ns ; S ; Y[9] ;
; N/A ; None ; 10.200 ns ; S ; Y[8] ;
; N/A ; None ; 10.200 ns ; S ; Y[7] ;
; N/A ; None ; 10.200 ns ; S ; Y[6] ;
; N/A ; None ; 10.200 ns ; S ; Y[5] ;
; N/A ; None ; 10.200 ns ; S ; Y[4] ;
; N/A ; None ; 10.200 ns ; S ; Y[3] ;
; N/A ; None ; 10.200 ns ; S ; Y[2] ;
; N/A ; None ; 10.200 ns ; S ; Y[1] ;
; N/A ; None ; 10.200 ns ; S ; Y[0] ;
; N/A ; None ; 10.000 ns ; B[15] ; Y[15] ;
; N/A ; None ; 10.000 ns ; A[15] ; Y[15] ;
; N/A ; None ; 10.000 ns ; B[14] ; Y[14] ;
; N/A ; None ; 10.000 ns ; A[14] ; Y[14] ;
; N/A ; None ; 10.000 ns ; B[13] ; Y[13] ;
; N/A ; None ; 10.000 ns ; A[13] ; Y[13] ;
; N/A ; None ; 10.000 ns ; B[12] ; Y[12] ;
; N/A ; None ; 10.000 ns ; A[12] ; Y[12] ;
; N/A ; None ; 10.000 ns ; B[11] ; Y[11] ;
; N/A ; None ; 10.000 ns ; A[11] ; Y[11] ;
; N/A ; None ; 10.000 ns ; B[10] ; Y[10] ;
; N/A ; None ; 10.000 ns ; A[10] ; Y[10] ;
; N/A ; None ; 10.000 ns ; B[9] ; Y[9] ;
; N/A ; None ; 10.000 ns ; A[9] ; Y[9] ;
; N/A ; None ; 10.000 ns ; B[8] ; Y[8] ;
; N/A ; None ; 10.000 ns ; A[8] ; Y[8] ;
; N/A ; None ; 10.000 ns ; B[7] ; Y[7] ;
; N/A ; None ; 10.000 ns ; A[7] ; Y[7] ;
; N/A ; None ; 10.000 ns ; B[6] ; Y[6] ;
; N/A ; None ; 10.000 ns ; A[6] ; Y[6] ;
; N/A ; None ; 10.000 ns ; B[5] ; Y[5] ;
; N/A ; None ; 10.000 ns ; A[5] ; Y[5] ;
; N/A ; None ; 10.000 ns ; B[4] ; Y[4] ;
; N/A ; None ; 10.000 ns ; A[4] ; Y[4] ;
; N/A ; None ; 10.000 ns ; B[3] ; Y[3] ;
; N/A ; None ; 10.000 ns ; A[3] ; Y[3] ;
; N/A ; None ; 10.000 ns ; B[2] ; Y[2] ;
; N/A ; None ; 10.000 ns ; A[2] ; Y[2] ;
; N/A ; None ; 10.000 ns ; B[1] ; Y[1] ;
; N/A ; None ; 10.000 ns ; A[1] ; Y[1] ;
; N/A ; None ; 10.000 ns ; B[0] ; Y[0] ;
; N/A ; None ; 10.000 ns ; A[0] ; Y[0] ;
+-------+-------------------+-----------------+-------+-------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Sun Dec 07 11:49:26 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off select_32 -c select_32
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Info: Longest tpd from source pin "S" to destination pin "Y[15]" is 10.200 ns
Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_72; Fanout = 32; PIN Node = 'S'
Info: 2: + IC(3.400 ns) + CELL(4.000 ns) = 8.600 ns; Loc. = LC37; Fanout = 1; COMB Node = 'Y~160'
Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 10.200 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'Y[15]'
Info: Total cell delay = 6.800 ns ( 66.67 % )
Info: Total interconnect delay = 3.400 ns ( 33.33 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 108 megabytes of memory during processing
Info: Processing ended: Sun Dec 07 11:49:28 2008
Info: Elapsed time: 00:00:02
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