library ieee;
use ieee.std_logic_1164.all;

entity select_32 is
	port(	A:in std_logic_vector(15 downto 0);
			B:in std_logic_vector(15 downto 0);
			S:in std_logic;
			Y:out std_logic_vector(15 downto 0));
end entity;

architecture bevi of select_32 is
	begin
	Y<=A when (S='0') else B;
end architecture;