?? select_32.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
entity select_32 is
port( A:in std_logic_vector(15 downto 0);
B:in std_logic_vector(15 downto 0);
S:in std_logic;
Y:out std_logic_vector(15 downto 0));
end entity;
architecture bevi of select_32 is
begin
Y<=A when (S='0') else B;
end architecture;
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