?? select_32.map.rpt
字號:
Analysis & Synthesis report for select_32
Sun Dec 07 11:49:19 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Dec 07 11:49:19 2008 ;
; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name ; select_32 ;
; Top-level Entity Name ; select_32 ;
; Family ; MAX3000A ;
; Total macrocells ; 16 ;
; Total pins ; 49 ;
+-----------------------------+------------------------------------------+
+---------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+------------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+------------------+---------------+
; Device ; EPM3256ATI144-10 ; ;
; Top-level entity name ; select_32 ; select_32 ;
; Family name ; MAX3000A ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Block Design Naming ; Auto ; Auto ;
+----------------------------------------------------------------------+------------------+---------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+---------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+---------------------------------+
; select_32.vhd ; yes ; User VHDL File ; D:/cpld/select_32/select_32.vhd ;
+----------------------------------+-----------------+-----------------+---------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 16 ;
; Total registers ; 0 ;
; I/O pins ; 49 ;
; Maximum fan-out node ; S ;
; Maximum fan-out ; 16 ;
; Total fan-out ; 64 ;
; Average fan-out ; 0.98 ;
+----------------------+----------------------+
+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+------------+------+---------------------+--------------+
; |select_32 ; 16 ; 49 ; |select_32 ; work ;
+----------------------------+------------+------+---------------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Sun Dec 07 11:49:17 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off select_32 -c select_32
Info: Found 2 design units, including 1 entities, in source file select_32.vhd
Info: Found design unit 1: select_32-bevi
Info: Found entity 1: select_32
Info: Elaborating entity "select_32" for the top level hierarchy
Info: Implemented 65 device resources after synthesis - the final resource count might be different
Info: Implemented 33 input pins
Info: Implemented 16 output pins
Info: Implemented 16 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Allocated 151 megabytes of memory during processing
Info: Processing ended: Sun Dec 07 11:49:19 2008
Info: Elapsed time: 00:00:02
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