`timescale 10ns/1nsmodule top_tb;reg  DIN,CLK,RESET;wire DOUT,DATA_EN,BIT_EN;miller_decode U1(            //inputs               .DIN(DIN),    // input miller encode serial              .CLK(CLK),    // system clk              .RESET(RESET),  // system reset            //outputs              .DOUT(DOUT),   // output miller decode serial              .DATA_EN(DATA_EN),// output enable              .BIT_EN(BIT_EN)  // bit effective enable                     );reg clock;parameter step=50;     // T_clock=step*10nsparameter A=16'b1111_1111_0000_0111;parameter B=16'b1111_1111_1111_1111;parameter C=16'b0000_0111_1111_1111;reg[16*11-1:0] frame1,frame2,frame3,frame4;reg[4*16*11+16*9-1:0] frame_total; // 1 start+ 8 signal +2 stop//reg[4*16*11+16-1:0] frame_total; //// input miller serial signalinitial begin    DIN=1;    frame1={C,A,B,C,A,B,A,A,B,C,B}; // 1001_0110    frame2={C,C,C,C,A,B,A,B,C,C,B}; // 0001_0100    frame3={C,A,B,A,B,C,A,B,A,B,B}; // 1010_0101    frame4={C,C,C,A,B,C,A,A,A,B,B}; // 0010_0111    frame_total={B,frame1,B,B,frame2,B,B,frame3,B,B,frame4,B,B}; // add B to stop   // frame_total={B,frame1,frame2,frame3,frame4};    end//// generate clock & resetinitialbegin  clock = 0;   forever  //#(16*step)  #(step/2) clock=~clock;           // 2MHzend//always #(step/2) clock =~clock;   // 2MHzinitialbegin        RESET = 0;  #step RESET = 1;  // 1 clock periodendinitial begin    #((4*16*11+16*9)*step) $stop;    //#((4*16*11+16)*step) $stop;end// inputalways @(negedge clock)begin    DIN<=frame_total[847];  // 847=4*16*11+16*9-1    //DIN<=frame_total[719];   // 719=4*16*11+16-1    frame_total<=(frame_total<<1);end// generate system clkalways @ (clock) //din orclockbegin  CLK = DIN & clock;  endendmodule