--------------------------------------------------------------------------------  This file is a part of the GRLIB VHDL IP LIBRARY--  Copyright (C) 2003, Gaisler Research----  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License as published by--  the Free Software Foundation; either version 2 of the License, or--  (at your option) any later version.----  This program is distributed in the hope that it will be useful,--  but WITHOUT ANY WARRANTY; without even the implied warranty of--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the--  GNU General Public License for more details.----  You should have received a copy of the GNU General Public License--  along with this program; if not, write to the Free Software--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA -----------------------------------------------------------------------------   -- Entity:      dcache-- File:        dcache.vhd-- Author:      Jiri Gaisler, Konrad Eisele - Gaisler Research-- Description: This unit implements the data cache controller.------------------------------------------------------------------------------  library ieee;use ieee.std_logic_1164.all;library techmap;use techmap.gencomp.all;library grlib;use grlib.amba.all;use grlib.sparc.all;use grlib.stdlib.all;library gaisler;use gaisler.libiu.all;use gaisler.libcache.all;use gaisler.mmuconfig.all;		use gaisler.mmuiface.all;		entity mmu_dcache is  generic (    dsu       : integer range 0 to 1  := 0;    drepl     : integer range 0 to 2  := 0;    dsets     : integer range 1 to 4  := 1;    dlinesize : integer range 4 to 8  := 4;    dsetsize  : integer range 1 to 256 := 1;    dsetlock  : integer range 0 to 1  := 0;    dsnoop    : integer range 0 to 6 := 0;    itlbnum   : integer range 2 to 64 := 8;    dtlbnum   : integer range 2 to 64 := 8;    tlb_type  : integer range 0 to 3 := 1;    memtech   : integer range 0 to NTECH := 0;    cached    : integer := 0);  port (    rst : in  std_logic;    clk : in  std_logic;    dci : in  dcache_in_type;    dco : out dcache_out_type;    ico : in  icache_out_type;    mcdi : out memory_dc_in_type;    mcdo : in  memory_dc_out_type;    ahbsi : in  ahb_slv_in_type;    dcrami : out dcram_in_type;    dcramo : in  dcram_out_type;    fpuholdn : in  std_logic;    mmudci : out mmudc_in_type;    mmudco : in mmudc_out_type;    sclk : in std_ulogic);end; architecture rtl of mmu_dcache isconstant DSNOOP2        : integer := conv_integer(conv_std_logic_vector(dsnoop,3) and conv_std_logic_vector(3,3));constant DSNOOP4        : integer := conv_integer(conv_std_logic_vector(dsnoop,3) and conv_std_logic_vector(4,3));  constant M_TLB_TYPE     : integer range 0 to 1 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(1,2));  -- eather split or combinedconstant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2));   -- fast writebufferconstant M_ENT_I        : integer range 2 to 64 := itlbnum;   -- icache tlb entries: numberconstant M_ENT_ILOG     : integer := log2(M_ENT_I);     -- icache tlb entries: address bitsconstant M_ENT_D        : integer range 2 to 64 := dtlbnum;   -- dcache tlb entries: numberconstant M_ENT_DLOG     : integer := log2(M_ENT_D);     -- dcache tlb entries: address bitsconstant M_ENT_C        : integer range 2 to 64 := M_ENT_I;   -- i/dcache tlb entries: numberconstant M_ENT_CLOG     : integer := M_ENT_ILOG;     -- i/dcache tlb entries: address bits  constant DLINE_BITS   : integer := log2(dlinesize);constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;constant LRR_BIT      : integer := TAG_HIGH + 1;constant TAG_LOW    : integer := DOFFSET_BITS + DLINE_BITS + 2;constant OFFSET_HIGH: integer := TAG_LOW - 1;constant OFFSET_LOW : integer := DLINE_BITS + 2;constant LINE_HIGH  : integer := OFFSET_LOW - 1;constant LINE_LOW   : integer := 2;constant LINE_ZERO  : std_logic_vector(DLINE_BITS-1 downto 0) := (others => '0');constant SETBITS : integer := log2x(DSETS); constant DLRUBITS  : integer := lru_table(DSETS);constant lram      : integer range 0 to 1 := 0;constant lramsize  : integer range 1 to 64 := 1;constant lramstart : integer range 0 to 255 := 16#00#;    constant LOCAL_RAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(lramstart, 8);constant DREAD_FAST  : boolean := false;constant DWRITE_FAST  : boolean := false;constant DCLOCK_BIT : integer := dsetlock;constant M_EN : boolean := true;constant DCREPLACE  : integer range 0 to 2  :=    drepl;constant DLINE_SIZE : integer := dlinesize;constant DEST_RW      : boolean := (syncram_dp_dest_rw_collision(memtech) = 1);type rdatatype is (dtag, ddata, dddata, dctx, icache, memory, sysr , misc, mmusnoop_dtag);  -- sources during cache readtype vmasktype is (clearone, clearall, merge, tnew);	-- valid bits operationtype valid_type is array (0 to DSETS-1) of std_logic_vector(dlinesize - 1 downto 0);type write_buffer_type is record			-- write buffer   addr, data1, data2 : std_logic_vector(31 downto 0);  size : std_logic_vector(1 downto 0);  asi  : std_logic_vector(3 downto 0);  read : std_logic;  lock : std_logic;end record;type dstatetype is (idle, wread, rtrans, wwrite, wtrans, wflush,                     asi_idtag,dblwrite, loadpend);type dcache_control_type is record			-- all registers  read : std_logic;					-- access direction  size : std_logic_vector(1 downto 0);			-- access size  req, burst, holdn, nomds, stpend  : std_logic;  xaddress : std_logic_vector(31 downto 0);		-- common address buffer  paddress : std_logic_vector(31 downto 0);		-- physical address buffer  faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0);	-- flush address  valid : valid_type; --std_logic_vector(DLINE_SIZE - 1 downto 0);	-- registered valid bits  dstate : dstatetype; 			                -- FSM  hit : std_logic;  flush		: std_logic;				-- flush in progress  flush2	: std_logic;				-- flush in progress  mexc 		: std_logic;				-- latched mexc  wb 		: write_buffer_type;			-- write buffer  asi  		: std_logic_vector(4 downto 0);  icenable	: std_logic;				-- icache diag access  rndcnt        : std_logic_vector(log2x(DSETS)-1 downto 0); -- replace counter  setrepl       : std_logic_vector(log2x(DSETS)-1 downto 0); -- set to replace  lrr           : std_logic;              dsuset        : std_logic_vector(log2x(DSETS)-1 downto 0);  lock          : std_logic;  lramrd : std_ulogic;  cctrl		   : cctrltype;  cctrlwr       : std_ulogic;  mmctrl1       : mmctrl_type1;  mmctrl1wr       : std_ulogic;    pflush        : std_logic;  pflushr       : std_logic;  pflushaddr    : std_logic_vector(VA_I_U downto VA_I_D);  pflushtyp     : std_logic;  vaddr         : std_logic_vector(31 downto 0);  ready         : std_logic;  wbinit        : std_logic;  cache         : std_logic;  su            : std_logic;  dblwdata      : std_logic;  trans_op      : std_logic;  flush_op      : std_logic;  diag_op       : std_logic;end record;type snoop_reg_type is record			-- snoop control registers  snoop   : std_logic;				-- snoop access to tags  writebp : std_logic_vector(0 to DSETS-1);		-- snoop write bypass  addr 	  : std_logic_vector(TAG_HIGH downto OFFSET_LOW);-- snoop tag  readbpx  : std_logic_vector(0 to DSETS-1);  -- possible write/read contentionend record;type snoop_hit_bits_type is array (0 to 2**DOFFSET_BITS-1) of std_logic_vector(0 to DSETS-1);type snoop_hit_reg_type is record  hit 	  : snoop_hit_bits_type;                              -- snoop hit bits    taddr	  : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);  -- saved tag address  set     : std_logic_vector(log2x(DSETS)-1 downto 0);        -- saved setend record;subtype lru_type is std_logic_vector(DLRUBITS-1 downto 0);type lru_array  is array (0 to 2**DOFFSET_BITS-1) of lru_type;  -- lru registerstype par_type is array (0 to DSETS-1) of std_logic_vector(1 downto 0);type lru_reg_type is record  write : std_logic;  waddr : std_logic_vector(DOFFSET_BITS-1 downto 0);  set   :  std_logic_vector(SETBITS-1 downto 0); --integer range 0 to DSETS-1;  lru   : lru_array;end record;subtype lock_type is std_logic_vector(0 to DSETS-1);function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector isvariable xlru : std_logic_vector(4 downto 0);variable set  : std_logic_vector(SETBITS-1 downto 0);variable xset : std_logic_vector(1 downto 0);variable unlocked : integer range 0 to DSETS-1;begin  set := (others => '0'); xlru := (others => '0'); xset := (others => '0');  xlru(DLRUBITS-1 downto 0) := lru;  if dsetlock = 1 then     unlocked := DSETS-1;    for i in DSETS-1 downto 0 loop      if lock(i) = '0' then unlocked := i; end if;    end loop;  end if;  case DSETS is  when 2 =>    if dsetlock = 1 then      if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;    else xset(0) := xlru(0); end if;  when 3 =>     if dsetlock = 1 then      xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);    else      xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);    end if;  when 4 =>    if dsetlock = 1 then      xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);    else      xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);    end if;      when others =>   end case;  set := xset(SETBITS-1 downto 0);  return(set);end;function lru_calc (lru : lru_type; set : integer) return lru_type isvariable new_lru : lru_type;variable xnew_lru: std_logic_vector(4 downto 0);variable xlru : std_logic_vector(4 downto 0);begin  new_lru := (others => '0'); xnew_lru := (others => '0');  xlru := (others => '0'); xlru(DLRUBITS-1 downto 0) := lru;  case DSETS is  when 2 =>     if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;  when 3 =>    xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);   when 4 =>     xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);  when others =>   end case;  new_lru := xnew_lru(DLRUBITS-1 downto 0);  return(new_lru);end;subtype word is std_logic_vector(31 downto 0);signal r, c : dcache_control_type;	-- r is registers, c is combinationalsignal rs, cs : snoop_reg_type;		-- rs is registers, cs is combinationalsignal rh, ch : snoop_hit_reg_type;	-- rs is registers, cs is combinationalsignal rl, cl : lru_reg_type;           -- rl is registers, cl is combinationalconstant ctbl : std_logic_vector(15 downto 0) :=  conv_std_logic_vector(cached, 16);begin  dctrl : process(rst, r, rs, rh, rl, dci, mcdo, ico, dcramo, ahbsi, fpuholdn, mmudco)  variable dcramov : dcram_out_type;  variable rdatasel : rdatatype;  variable maddress : std_logic_vector(31 downto 0);  variable maddrlow : std_logic_vector(1 downto 0);  variable edata : std_logic_vector(31 downto 0);  variable size : std_logic_vector(1 downto 0);  variable read : std_logic;  variable twrite, tpwrite, tdiagwrite, ddiagwrite, dwrite : std_logic;  variable taddr : std_logic_vector(OFFSET_HIGH  downto LINE_LOW); -- tag address  variable newtag : std_logic_vector(TAG_HIGH  downto TAG_LOW); -- new tag  variable newptag : std_logic_vector(TAG_HIGH  downto TAG_LOW); -- new tag  variable align_data : std_logic_vector(31 downto 0); -- aligned data  variable ddatainv, rdatav, align_datav : cdatatype;  variable rdata : std_logic_vector(31 downto 0);  variable vmaskraw : std_logic_vector((dlinesize -1) downto 0);  variable vmask : valid_type; --std_logic_vector((dlinesize -1) downto 0);  variable ivalid : std_logic_vector((dlinesize -1) downto 0);  variable vmaskdbl : std_logic_vector((dlinesize/2 -1) downto 0);  variable enable, senable, scanen : std_logic_vector(0 to 3);  variable mds : std_logic;  variable mexc : std_logic;  variable hit, valid, validraw, forcemiss : std_logic;  variable flush    : std_logic;  variable iflush   : std_logic;  variable v : dcache_control_type;  variable eholdn : std_logic;				-- external hold  variable tparerr, dparerr  : std_logic_vector(0 to DSETS-1);  variable snoopwe : std_logic;  variable hcache   : std_logic;  variable snoopaddr: std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);  variable vs : snoop_reg_type;  variable vh : snoop_hit_reg_type;  variable dsudata   : std_logic_vector(31 downto 0);  variable set : integer range 0 to DSETS-1;  variable ddset : integer range 0 to MAXSETS-1;  variable snoopset : integer range 0 to DSETS-1;  variable validv, hitv, validrawv : std_logic_vector(0 to MAXSETS-1);  variable csnoopwe : std_logic_vector(0 to MAXSETS-1);  variable ctwrite, ctpwrite, cdwrite : std_logic_vector(0 to MAXSETS-1);  variable vset, setrepl  : std_logic_vector(log2x(DSETS)-1 downto 0);  variable wlrr : std_logic_vector(0 to MAXSETS-1);  variable vl : lru_reg_type;  variable diagset : std_logic_vector(TAG_LOW + SETBITS -1 downto TAG_LOW);  variable lock : std_logic_vector(0 to DSETS-1);  variable wlock : std_logic_vector(0 to MAXSETS-1);  variable snoopset2, rdsuset : integer range 0 to DSETS-1;  variable snoophit : std_logic_vector(0 to DSETS-1);  variable snoopval : std_logic;  variable tag : cdatatype; --std_logic_vector(31  downto 0);  variable ptag : cdatatype; --std_logic_vector(31  downto 0);  variable ctx : ctxdatatype;  variable miscdata  : std_logic_vector(31 downto 0);  variable mmudiagaddr  : std_logic_vector(2 downto 0);  variable pflush : std_logic;  variable pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);  variable pflushtyp : std_logic;  variable pftag : std_logic_vector(31 downto 2);  variable mmuwdata : std_logic_vector(31 downto 0);  variable mmudci_fsread, tagclear : std_logic;  variable mmudci_trans_op : std_logic;  variable mmudci_flush_op : std_logic;  variable mmudci_wb_op : std_logic;  variable mmudci_diag_op : std_logic;  variable mmudci_su : std_logic;  variable mmudci_read : std_logic;  variable mmuregw, su : std_logic;  variable mmuisdis : std_logic;  variable readbp : std_logic_vector(0 to DSETS-1);  variable rbphit, sidle : std_logic;  variable mmudci_transdata_data : std_logic_vector(31 downto 0);  variable paddress : std_logic_vector(31 downto 0);		-- physical address buffer  begin-- init local variables    v := r; vs := rs; vh := rh; dcramov := dcramo; vl := rl;    vl.write := '0'; v.cctrlwr := '0'; v.mmctrl1wr := '0';    v.flush2 := r.flush; sidle := '0';    if ((dci.eenaddr or dci.enaddr) = '1') or (r.dstate /= idle) or        ((dsu = 1) and (dci.dsuen = '1')) or (r.flush = '1')  or	(is_fpga(memtech) = 1)    then      enable := (others => '1');    else enable := (others => '0'); end if;    tagclear := '0'; mmuisdis := '0';    if (not M_EN) or ((r.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then      mmuisdis := '1';    end if;        if (mmuisdis = '1') then paddress := r.xaddress;    else paddress := r.paddress; end if;    mds := '1'; dwrite := '0'; twrite := '0'; tpwrite := '0';     ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';    flush := '0'; v.icenable := '0'; iflush := '0';    eholdn := ico.hold and fpuholdn; ddset := 0; vset := (others => '0');    tparerr  := (others => '0'); dparerr  := (others => '0');     vs.snoop := '0'; vs.writebp := (others => '0'); snoopwe := '0';    snoopaddr := ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW);    hcache := '0'; rdsuset := 0;     validv := (others => '0'); validrawv := (others => '0');    hitv := (others => '0'); ivalid := (others => '0');    miscdata := (others => '0'); pflush := '0';    pflushaddr := dci.maddress(VA_I_U downto VA_I_D); pflushtyp := PFLUSH_PAGE;    pftag := (others => '0');      mmudiagaddr := (others => '0'); mmuregw := '0'; mmuwdata := (others => '0');    mmudci_fsread := '0';    ddatainv := (others => (others => '0')); tag := (others => (others => '0')); ptag := (others => (others => '0'));    ctx := (others => (others => '0')); vs.readbpx := (others => '0'); rbphit := '0';