newptag(TAG_HIGH downto TAG_LOW) := (others => '0');        v.trans_op := r.trans_op and (not mmudco.grant);    v.flush_op := r.flush_op and (not mmudco.grant);    v.diag_op := r.diag_op and (not mmudco.grant);    mmudci_trans_op := r.trans_op;    mmudci_flush_op := r.flush_op;    mmudci_diag_op := r.diag_op;    mmudci_wb_op := '0';    mmudci_transdata_data := r.vaddr;        mmudci_su := '0'; mmudci_read := '0'; su := '0';    if (not M_EN) or (r.mmctrl1.e = '0') then v.cache := '1'; end if;        rdatasel := ddata;	-- read data from cache as default    senable := (others => '0'); scanen := (others => mcdo.scanen);        set := 0; snoopset := 0;  csnoopwe := (others => '0');    ctwrite := (others => '0'); ctpwrite := (others => '0'); cdwrite := (others => '0');    wlock := (others => '0');    for i in 0 to DSETS-1 loop wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;     wlrr := (others => '0');    for i in 0 to 3 loop wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS); end loop;         if (DSETS > 1) then setrepl := r.setrepl; else setrepl := (others => '0'); end if;    -- random replacement counter    if DSETS > 1 then      if conv_integer(r.rndcnt) = (DSETS - 1) then v.rndcnt := (others => '0');      else v.rndcnt := r.rndcnt + 1; end if;    end if;-- generate lock bits    lock := (others => '0');    if DCLOCK_BIT = 1 then       for i in 0 to DSETS-1 loop lock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;    end if;    -- AHB snoop handling    if DSNOOP2 /= 0 then      -- snoop on NONSEQ or SEQ and first word in cache line      -- do not snoop during own transfers or during cache flush      if (ahbsi.hready and ahbsi.hwrite and not mcdo.bg) = '1' and         ((ahbsi.htrans = HTRANS_NONSEQ) or 	    ((ahbsi.htrans = HTRANS_SEQ) and 	     (ahbsi.haddr(LINE_HIGH downto LINE_LOW) = LINE_ZERO)))       then	vs.snoop := r.cctrl.dsnoop;-- and not r.mmctrl1.e;        vs.addr := ahbsi.haddr(TAG_HIGH downto OFFSET_LOW);       end if;      for i in 0 to DSETS-1 loop senable(i) := vs.snoop or rs.snoop; end loop;              readbp := (others => '0');      if (paddress(TAG_HIGH downto OFFSET_LOW) = rs.addr(TAG_HIGH downto OFFSET_LOW)) then rbphit := '1'; end if;      for i in 0 to DSETS-1 loop        if (rs.readbpx(i) and rbphit) = '1' then readbp(i) := '1'; end if;      end loop;              -- clear valid bits on snoop hit (or set hit bits)      for i in DSETS-1 downto 0 loop        if ((rs.snoop and (not mcdo.ba) and not r.flush) = '1')           and ((dcramov.stag(i)(TAG_HIGH downto TAG_LOW) = rs.addr(TAG_HIGH downto TAG_LOW)) or (readbp(i) = '1'))        then          if DSNOOP2 = 2 then            vh.hit(conv_integer(rs.addr(OFFSET_HIGH downto OFFSET_LOW)))(i) := '1';          else            snoopaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW);            snoopwe := '1'; snoopset := i;                  end if;        end if;      -- bypass tag data on read/write contention        if (DSNOOP2 /= 2) and (rs.writebp(i) = '1') then           dcramov.tag(i)(TAG_HIGH downto TAG_LOW) := rs.addr(TAG_HIGH downto TAG_LOW);          dcramov.tag(i)(dlinesize-1 downto 0) := zero32(dlinesize-1 downto 0);        end if;      end loop;    end if;-- generate access parameters during pipeline stall    if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then      taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);    elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')    then      taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);    else      taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);    end if;        if (dci.write or not r.holdn) = '1' then      maddress := r.xaddress(31 downto 0); --signed := r.signed;       read := r.read; size := r.size; edata := dci.maddress;      mmudci_su := r.su; mmudci_read := r.read;    else      maddress := dci.maddress(31 downto 0); --signed := dci.signed;       read := dci.read; size := dci.size; edata := dci.edata;      mmudci_su := dci.msu; mmudci_read := dci.read;    end if;    newtag := dci.maddress(TAG_HIGH downto TAG_LOW);    newptag := dci.maddress(TAG_HIGH downto TAG_LOW);    vl.waddr := maddress(OFFSET_HIGH downto OFFSET_LOW);  -- lru write address-- generate cache hit and valid bits    if cached /= 0 then hcache := ctbl(conv_integer(dci.maddress(31 downto 28)));    else hcache := '1'; end if;    forcemiss := not dci.asi(3); hit := '0'; set := 0;     snoophit := (others => '0'); snoopval := '1';    for i in DSETS-1 downto 0 loop      if DSNOOP2 = 2 then        snoophit(i) := rh.hit(conv_integer(rh.taddr))(i);      end if;      if (dcramov.tag(i)(TAG_HIGH downto TAG_LOW) = dci.maddress(TAG_HIGH downto TAG_LOW))        and ((dcramov.ctx(i) = r.mmctrl1.ctx) or (r.mmctrl1.e = '0'))      then hitv(i) := hcache; end if;      validrawv(i) := hitv(i) and (not r.flush) and (not r.flush2) and (not snoophit(i)) and	genmux(dci.maddress(LINE_HIGH downto LINE_LOW), dcramov.tag(i)(dlinesize-1 downto 0));      validv(i) :=  validrawv(i);      snoopval := snoopval and not snoophit(i);    end loop;                  hit := orv(hitv) and not r.flush and (not r.flush2);    -- cache hit disabled if mmu-enabled but off or BYPASS    if (M_EN) and (dci.asi(4 downto 0) = ASI_MMU_BP) then  -- or (r.mmctrl1.e = '0')      hit := '0';    end if;        validraw := orv(validrawv);    valid := orv(validv);    if DSETS > 1 then       for i in DSETS-1 downto 0 loop         if hitv(i) = '1' then	  vset := conv_std_logic_vector(i, SETBITS);        end if;      end loop;      set := conv_integer(vset);    else set := 0; end if;    if (dci.dsuen = '1') then diagset := r.xaddress(TAG_LOW+SETBITS-1 downto TAG_LOW);                                                    else diagset := maddress(TAG_LOW + SETBITS - 1 downto TAG_LOW); end if;    case DSETS is    when 1 => ddset := 0;    when 3 => if conv_integer(diagset) < 3 then ddset := conv_integer(diagset); end if;    when others => ddset := conv_integer(diagset);     end case;        if ((r.holdn and dci.enaddr) = '1')  and (r.dstate = idle) then        v.hit := hit; v.xaddress := dci.maddress;	v.read := dci.read; v.size := dci.size;	v.asi := dci.asi(4 downto 0);  	--v.signed := dci.signed;        v.su := dci.msu;    end if;-- Store buffer    if mcdo.ready = '1' then      v.wb.addr(2) := r.wb.addr(2) or (r.wb.size(0) and r.wb.size(1));      if r.stpend = '1' then        v.stpend := r.req; v.wb.data1 := r.wb.data2; 	v.wb.lock := r.wb.lock and r.req;      end if;    end if;    if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;    if (mcdo.grant and not r.wb.read and r.req) = '1' then v.wb.lock := '0'; end if;    -- cache freeze operation    if (r.cctrl.ifrz and dci.intack and r.cctrl.ics(0)) = '1' then      v.cctrl.ics := "01";    end if;    if (r.cctrl.dfrz and dci.intack and r.cctrl.dcs(0)) = '1' then      v.cctrl.dcs := "01";    end if;            if r.cctrlwr = '1' then    if (r.xaddress(7 downto 2) = "000000") and (dci.read = '0') then      v.cctrl.dsnoop := dci.maddress(23);      flush        := dci.maddress(22);      iflush       := dci.maddress(21);      v.cctrl.burst:= dci.maddress(16);      v.cctrl.dfrz := dci.maddress(5);      v.cctrl.ifrz := dci.maddress(4);      v.cctrl.dcs  := dci.maddress(3 downto 2);      v.cctrl.ics  := dci.maddress(1 downto 0);                  end if;    end if;    if (dsu = 1) and (dci.dsuen = '1') then      mmuwdata := dci.maddress;    else      mmuwdata := dci.edata;    end if;          mmudiagaddr := dci.maddress(CNR_U downto CNR_D);    if r.mmctrl1wr = '1' then      mmudiagaddr := r.xaddress(CNR_U downto CNR_D);  -- defer match sram out      if (dci.read = '0') then        mmuwdata := dci.maddress;        mmuregw := '1';        end if;    end if;    -- main Dcache state machine    case r.dstate is    when idle =>			-- Idle state      if (M_TLB_FASTWRITE /= 0) then        mmudci_transdata_data := dci.maddress;      end if;      sidle := '1';      if (snoopval = '1') then        for i in 0 to DSETS-1 loop          v.valid(i) := dcramov.tag(i)(dlinesize-1 downto 0);	end loop;      else v.valid := (others => (others => '0')); end if;      v.nomds := r.nomds and not eholdn; --v.valid := dcramov.dtramout(set).valid;      if (r.stpend  = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue	v.wb.addr := dci.maddress; v.wb.size := dci.size; 	v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock;	v.wb.asi := dci.asi(3 downto 0);         if ((M_EN) and (dci.asi(4 downto 0) /= ASI_MMU_BP) and (r.mmctrl1.e = '1') and (M_TLB_FASTWRITE /= 0) ) then          v.wb.addr := mmudco.wbtransdata.data;          newptag := mmudco.wbtransdata.data(TAG_HIGH downto TAG_LOW);        end if;      end if;      if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify	case dci.asi(4 downto 0) is 	when ASI_SYSR => rdatasel := sysr;		when ASI_DTAG => rdatasel := dtag;	when ASI_DDATA => rdatasel := dddata;	when ASI_DCTX => rdatasel := dctx;        when ASI_MMUREGS => rdatasel := misc;  	when ASI_MMUSNOOP_DTAG => rdatasel := mmusnoop_dtag;	when others =>	end case;      end if;      if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then	case dci.asi(4 downto 0) is	when ASI_SYSR =>		-- system registers          if (dsu = 0) or (dci.dsuen = '0') then            if (dci.maddress(7 downto 2) = "000000") and (dci.read = '0') then              v.cctrl.dsnoop := dci.edata(23);              flush        := dci.edata(22);              iflush       := dci.edata(21);              v.cctrl.burst:= dci.edata(16);              v.cctrl.dfrz := dci.edata(5);              v.cctrl.ifrz := dci.edata(4);              v.cctrl.dcs  := dci.edata(3 downto 2);              v.cctrl.ics  := dci.edata(1 downto 0);            end if;          else            v.cctrlwr := not dci.read;          end if;        when ASI_MMUREGS =>          if (dsu = 0) or dci.dsuen = '0' then            if M_EN then--              rdatasel := misc;               -- clean fault valid bit              if dci.read = '1' then                case dci.maddress(CNR_U downto CNR_D) is                  when CNR_F =>                    mmudci_fsread := '1';                  when others => null;                end case;              else                mmuregw := '1';              end if;            end if;          else            v.mmctrl1wr := not dci.read and not (r.mmctrl1wr and dci.dsuen);          end if;	when ASI_ITAG | ASI_IDATA | ASI_ICTX =>		-- Read/write Icache tags          -- CTX write has to be done through ctxnr & ASI_ITAG	  if (ico.flush = '1') or (dci.asi(4) = '1') then mexc := '1'; 	 else v.dstate := asi_idtag; v.holdn := '0'; end if; 	when ASI_DFLUSH =>		-- flush data cache	  if dci.read = '0' then flush := '1'; end if; 	when ASI_DDATA =>		-- Read/write Dcache data 	  if (dci.size /= "10") or (r.flush = '1') then -- only word access is allowed 	    mexc := '1'; 	  elsif (dci.read = '0') then 	    dwrite := '1'; ddiagwrite := '1'; 	  end if; 	when ASI_DTAG =>		-- Read/write Dcache tags 	  if (dci.size /= "10") or (r.flush = '1') then -- allow only word access 	    mexc := '1'; 	  elsif (dci.read = '0') then 	    twrite := '1'; tdiagwrite := '1'; 	  end if;        when ASI_MMUSNOOP_DTAG =>	-- Read/write MMU physical snoop tags          if M_EN then          snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW);          if (dci.size /= "10") or (r.flush = '1') then -- allow only word access 	    mexc := '1'; 	  elsif (dci.read = '0') then 	    tpwrite := '1'; tdiagwrite := '1'; 	  end if; 	  end if;        when ASI_DCTX =>          -- write has to be done through ctxnr & ASI_DTAG          if (dci.size /= "10") or (r.flush = '1') or (dci.read = '0') then -- allow only word access 	    mexc := '1'; 	  end if;        when ASI_FLUSH_PAGE => -- i/dcache flush page          if M_EN then            if dci.read = '0' then              flush := '1'; iflush := '1'; --pflush := '1'; pflushtyp := PFLUSH_PAGE;            end if; 	  end if;        when ASI_FLUSH_CTX => -- i/dcache flush ctx          if M_EN then            if dci.read = '0' then              flush := '1'; iflush := '1'; --pflush := '1'; pflushtyp := PFLUSH_CTX;            end if;          end if;        when ASI_MMUFLUSHPROBE =>          if M_EN then            if dci.read = '0' then      -- flush              mmudci_flush_op := '1';              v.flush_op := not mmudco.grant;              v.dstate := wflush;              v.vaddr := dci.maddress; v.holdn := '0'; flush := '1'; iflush := '1';            end if;          end if;        when ASI_MMU_DIAG =>          if dci.read = '0' then      -- diag access            mmudci_diag_op := '1';            v.diag_op := not mmudco.grant;            v.vaddr := dci.maddress;          end if;        when others =>	  if dci.read = '1' then	-- read access            --if (not ((mcdo.dcs(0) = '1')             if (not ((r.cctrl.dcs(0) = '1') 	       and ((hit and valid and not forcemiss) = '1')))	    then	-- read miss	      v.holdn := '0'; v.dstate := wread; v.ready := '0'; v.cache := '1';              if (not M_EN) or                ((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0'))              then                -- cache disabled if mmu-enabled but off or BYPASS                if (M_EN) then v.cache := '0'; end if;                                if ((r.stpend  = '0') or ((mcdo.ready and not r.req) = '1'))                then	-- wait for store queue                                    v.req := '1';                  v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);                end if;              else                -- ## mmu case >                if (r.stpend  = '0') or ((mcdo.ready and not r.req)= '1')                then                  v.wbinit := '1';     -- wb init in idle                  v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);                else                  v.wbinit := '0';                end if;                                mmudci_trans_op := '1';  -- start translation                v.trans_op := not mmudco.grant;                v.vaddr := dci.maddress;                 v.dstate := rtrans;                -- ## < mmu case               end if;                          else       -- read hit              if (DSETS > 1) and (DCREPLACE = lru) then vl.write := '1'; end if;            end if;            	  else			-- write access            v.ready := '0';            if (not M_EN) or                            ((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then                                          if (r.stpend  = '0') or ((mcdo.ready and not r.req)= '1') then                v.req := '1'; v.stpend := '1';                 v.burst := dci.size(1) and dci.size(0);                if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store	                    else		-- wait for store queue                v.dstate := wwrite; v.holdn := '0';