--------------------------------------------------------------------------------  This file is a part of the GRLIB VHDL IP LIBRARY--  Copyright (C) 2003, Gaisler Research----  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License as published by--  the Free Software Foundation; either version 2 of the License, or--  (at your option) any later version.----  This program is distributed in the hope that it will be useful,--  but WITHOUT ANY WARRANTY; without even the implied warranty of--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the--  GNU General Public License for more details.----  You should have received a copy of the GNU General Public License--  along with this program; if not, write to the Free Software--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA -----------------------------------------------------------------------------   -- Entity:      dcache-- File:        dcache.vhd-- Author:      Jiri Gaisler - Gaisler Research-- Modified:    Edvin Catovic - Gaisler Research-- Description: This unit implements the data cache controller.------------------------------------------------------------------------------  library ieee;use ieee.std_logic_1164.all;library techmap;use techmap.gencomp.all;library grlib;use grlib.amba.all;use grlib.sparc.all;use grlib.stdlib.all;library gaisler;use gaisler.libiu.all;use gaisler.libcache.all;entity dcache is  generic (    dsu       : integer range 0 to 1  := 0;    dcen      : integer range 0 to 1  := 0;    drepl     : integer range 0 to 2  := 0;    dsets     : integer range 1 to 4  := 1;    dlinesize : integer range 4 to 8  := 4;    dsetsize  : integer range 1 to 256 := 1;    dsetlock  : integer range 0 to 1  := 0;    dsnoop    : integer range 0 to 6 := 0;    dlram      : integer range 0 to 1 := 0;    dlramsize  : integer range 1 to 512 := 1;    dlramstart : integer range 0 to 255 := 16#8f#;    ilram      : integer range 0 to 1 := 0;    ilramstart : integer range 0 to 255 := 16#8e#;    memtech    : integer range 0 to NTECH := 0;    cached     : integer := 0);  port (    rst : in  std_ulogic;    clk : in  std_ulogic;    dci : in  dcache_in_type;    dco : out dcache_out_type;    ico : in  icache_out_type;    mcdi : out memory_dc_in_type;    mcdo : in  memory_dc_out_type;    ahbsi : in  ahb_slv_in_type;    dcrami : out dcram_in_type;    dcramo : in  dcram_out_type;    fpuholdn : in  std_ulogic;    sclk : in std_ulogic);end; architecture rtl of dcache isconstant DLINE_BITS   : integer := log2(dlinesize);constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;constant LRR_BIT      : integer := TAG_HIGH + 1;constant TAG_LOW    : integer := DOFFSET_BITS + DLINE_BITS + 2;constant OFFSET_HIGH: integer := TAG_LOW - 1;constant OFFSET_LOW : integer := DLINE_BITS + 2;constant LINE_HIGH  : integer := OFFSET_LOW - 1;constant LINE_LOW   : integer := 2;constant LINE_ZERO  : std_logic_vector(DLINE_BITS-1 downto 0) := (others => '0');constant SETBITS : integer := log2x(DSETS); constant DLRUBITS  : integer := lru_table(DSETS);constant LOCAL_RAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(dlramstart, 8);constant ILRAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(ilramstart, 8);constant DREAD_FAST  : boolean := false;constant DWRITE_FAST  : boolean := false;constant DEST_RW      : boolean := (syncram_dp_dest_rw_collision(memtech) = 1);type rdatatype is (dtag, ddata, dddata, icache, memory, sysr);  -- sources during cache readtype vmasktype is (clearone, clearall, merge, tnew);	-- valid bits operationtype valid_type is array (0 to DSETS-1) of std_logic_vector(dlinesize - 1 downto 0);type write_buffer_type is record			-- write buffer   addr, data1, data2 : std_logic_vector(31 downto 0);  size : std_logic_vector(1 downto 0);  asi  : std_logic_vector(3 downto 0);  read : std_ulogic;  lock : std_ulogic;end record;type dcache_control_type is record			-- all registers  read : std_ulogic;					-- access direction  size : std_logic_vector(1 downto 0);			-- access size  req, burst, holdn, nomds, stpend  : std_ulogic;  xaddress : std_logic_vector(31 downto 0);		-- common address buffer  faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0);	-- flush address  valid : valid_type; --std_logic_vector(dlinesize - 1 downto 0);	-- registered valid bits  dstate : std_logic_vector(2 downto 0);			-- FSM vector  hit : std_ulogic;  flush		: std_ulogic;				-- flush in progress  flush2	: std_ulogic;				-- flush in progress  mexc 		: std_ulogic;				-- latched mexc  wb 		: write_buffer_type;			-- write buffer  asi  		: std_logic_vector(3 downto 0);  icenable	: std_ulogic;				-- icache diag access  rndcnt        : std_logic_vector(log2x(DSETS)-1 downto 0); -- replace counter  setrepl       : std_logic_vector(log2x(DSETS)-1 downto 0); -- set to replace  lrr           : std_ulogic;              dsuset        : std_logic_vector(log2x(DSETS)-1 downto 0);  lock          : std_ulogic;  lramrd : std_ulogic;  ilramen : std_ulogic;  cctrl		: cctrltype;  cctrlwr       : std_ulogic;  forcemiss 	: std_ulogic;end record;type snoop_reg_type is record			-- snoop control registers  snoop   : std_ulogic;				-- snoop access to tags  writebp : std_logic_vector(0 to DSETS-1);		-- snoop write bypass  addr 	  : std_logic_vector(TAG_HIGH downto OFFSET_LOW);-- snoop tag  readbpx  : std_logic_vector(0 to DSETS-1);  -- possible write/read contention    end record;type snoop_hit_bits_type is array (0 to 2**DOFFSET_BITS-1) of std_logic_vector(0 to DSETS-1);type snoop_hit_reg_type is record  hit 	  : snoop_hit_bits_type;                              -- snoop hit bits    taddr	  : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);  -- saved tag address  set     : std_logic_vector(log2x(DSETS)-1 downto 0);        -- saved setend record;subtype lru_type is std_logic_vector(DLRUBITS-1 downto 0);type lru_array  is array (0 to 2**DOFFSET_BITS-1) of lru_type;  -- lru registerstype par_type is array (0 to DSETS-1) of std_logic_vector(1 downto 0);type lru_reg_type is record  write : std_ulogic;  waddr : std_logic_vector(DOFFSET_BITS-1 downto 0);  set   :  std_logic_vector(SETBITS-1 downto 0); --integer range 0 to DSETS-1;  lru   : lru_array;end record;subtype lock_type is std_logic_vector(0 to DSETS-1);function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector isvariable xlru : std_logic_vector(4 downto 0);variable set  : std_logic_vector(SETBITS-1 downto 0);variable xset : std_logic_vector(1 downto 0);variable unlocked : integer range 0 to DSETS-1;begin  set := (others => '0'); xlru := (others => '0'); xset := (others => '0');  xlru(DLRUBITS-1 downto 0) := lru;  if dsetlock = 1 then     unlocked := DSETS-1;    for i in DSETS-1 downto 0 loop      if lock(i) = '0' then unlocked := i; end if;    end loop;  end if;  case DSETS is  when 2 =>    if dsetlock = 1 then      if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;    else xset(0) := xlru(0); end if;  when 3 =>     if dsetlock = 1 then      xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);    else      xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);    end if;  when 4 =>    if dsetlock = 1 then      xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);    else      xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);    end if;      when others =>   end case;  set := xset(SETBITS-1 downto 0);  return(set);end;function lru_calc (lru : lru_type; set : integer) return lru_type isvariable new_lru : lru_type;variable xnew_lru: std_logic_vector(4 downto 0);variable xlru : std_logic_vector(4 downto 0);begin  new_lru := (others => '0'); xnew_lru := (others => '0');  xlru := (others => '0'); xlru(DLRUBITS-1 downto 0) := lru;  case DSETS is  when 2 =>     if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;  when 3 =>    xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);   when 4 =>     xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);  when others =>   end case;  new_lru := xnew_lru(DLRUBITS-1 downto 0);  return(new_lru);end;subtype word is std_logic_vector(31 downto 0);signal r, c : dcache_control_type;	-- r is registers, c is combinationalsignal rs, cs : snoop_reg_type;		-- rs is registers, cs is combinationalsignal rh, ch : snoop_hit_reg_type;	-- rs is registers, cs is combinationalsignal rl, cl : lru_reg_type;           -- rl is registers, cl is combinationalconstant ctbl : std_logic_vector(15 downto 0) :=  conv_std_logic_vector(cached, 16);begin  dctrl : process(rst, r, rs, rh, rl, dci, mcdo, ico, dcramo, ahbsi, fpuholdn)  variable dcramov : dcram_out_type;  variable rdatasel : rdatatype;  variable maddress : std_logic_vector(31 downto 0);  variable maddrlow : std_logic_vector(1 downto 0);  variable edata : std_logic_vector(31 downto 0);  variable size : std_logic_vector(1 downto 0);  variable read : std_ulogic;  variable twrite, tdiagwrite, ddiagwrite, dwrite : std_ulogic;  variable taddr : std_logic_vector(OFFSET_HIGH  downto LINE_LOW); -- tag address  variable newtag : std_logic_vector(TAG_HIGH  downto TAG_LOW); -- new tag  variable align_data : std_logic_vector(31 downto 0); -- aligned data--  variable ddatain : std_logic_vector(31 downto 0);  variable ddatainv, rdatav, align_datav : cdatatype;  variable vmaskraw : std_logic_vector((dlinesize -1) downto 0);  variable vmask : valid_type; --std_logic_vector((dlinesize -1) downto 0);  variable ivalid : std_logic_vector((dlinesize -1) downto 0);  variable vmaskdbl : std_logic_vector((dlinesize/2 -1) downto 0);  variable enable, senable, scanen : std_logic_vector(0 to 3);  variable mds : std_ulogic;  variable mexc : std_ulogic;  variable hit, valid, validraw, forcemiss : std_ulogic;  variable flush    : std_ulogic;  variable iflush   : std_ulogic;  variable v : dcache_control_type;  variable eholdn : std_ulogic;				-- external hold  variable snoopwe  : std_ulogic;  variable hcache   : std_ulogic;  variable lramcs, lramen, lramrd, lramwr, ilramen  : std_ulogic;  variable snoopaddr: std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);  variable vs : snoop_reg_type;  variable vh : snoop_hit_reg_type;  variable dsudata   : std_logic_vector(31 downto 0);  variable set : integer range 0 to DSETS-1;  variable ddset : integer range 0 to MAXSETS-1;  variable snoopset : integer range 0 to DSETS-1;  variable validv, hitv, validrawv : std_logic_vector(0 to MAXSETS-1);  variable csnoopwe : std_logic_vector(0 to MAXSETS-1);  variable ctwrite, cdwrite : std_logic_vector(0 to MAXSETS-1);  variable vset, setrepl  : std_logic_vector(log2x(DSETS)-1 downto 0);  variable wlrr : std_logic_vector(0 to 3);  variable vl : lru_reg_type;  variable diagset : std_logic_vector(TAG_LOW + SETBITS -1 downto TAG_LOW);  variable lock : std_logic_vector(0 to DSETS-1);  variable wlock : std_logic_vector(0 to MAXSETS-1);  variable snoophit : std_logic_vector(0 to DSETS-1);  variable snoopval : std_ulogic;  variable snoopset2 : integer range 0 to DSETS-1;  variable laddr : std_logic_vector(31  downto 0); -- local ram addr  variable tag : cdatatype; --std_logic_vector(31  downto 0);  variable rlramrd : std_ulogic;  variable readbp : std_logic_vector(0 to DSETS-1);  variable rbphit, sidle : std_logic;    begin-- init local variables    v := r; vs := rs; vh := rh; dcramov := dcramo; vl := rl;    vl.write := '0'; lramen := '0'; lramrd := '0'; lramwr := '0';     lramcs := '0'; laddr := (others => '0'); v.cctrlwr := '0';    ilramen := '0'; sidle := '0';        if ((dci.eenaddr or dci.enaddr) = '1') or (r.dstate /= "000") or        ((dsu = 1) and (dci.dsuen = '1')) or (r.flush = '1') or	(is_fpga(memtech) = 1)    then      enable := (others => '1');    else enable := (others => '0'); end if;    mds := '1'; dwrite := '0'; twrite := '0';     ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';    flush := '0'; v.icenable := '0'; iflush := '0';    eholdn := ico.hold and fpuholdn; ddset := 0; vset := (others => '0');    vs.snoop := '0'; vs.writebp := (others => '0'); snoopwe := '0';    snoopaddr := ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW);    hcache := '0';     validv := (others => '0'); validrawv := (others => '0');    hitv := (others => '0'); ivalid := (others => '0');    if (dlram = 1) then rlramrd := r.lramrd; else rlramrd := '0'; end if;    ddatainv := (others => (others => '0')); tag := (others => (others => '0'));    v.flush2 := r.flush;    rdatasel := ddata;	-- read data from cache as default    vs.readbpx := (others => '0'); rbphit := '0';    senable := (others => '0'); scanen := (others => mcdo.scanen);    set := 0; snoopset := 0;  csnoopwe := (others => '0');    ctwrite := (others => '0'); cdwrite := (others => '0');    wlock := (others => '0');    for i in 0 to DSETS-1 loop wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;     wlrr := (others => '0');    for i in 0 to 3 loop wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS); end loop;         if (DSETS > 1) then setrepl := r.setrepl; else setrepl := (others => '0'); end if;    -- random replacement counter    if DSETS > 1 then      if conv_integer(r.rndcnt) = (DSETS - 1) then v.rndcnt := (others => '0');      else v.rndcnt := r.rndcnt + 1; end if;    end if;-- generate lock bits    lock := (others => '0');    if dsetlock = 1 then       for i in 0 to DSETS-1 loop lock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;    end if;    -- AHB snoop handling    if (DSNOOP /= 0) then      -- snoop on NONSEQ or SEQ and first word in cache line      -- do not snoop during own transfers or during cache flush      if (ahbsi.hready and ahbsi.hwrite and not mcdo.bg) = '1' and         ((ahbsi.htrans = HTRANS_NONSEQ) or 	    ((ahbsi.htrans = HTRANS_SEQ) and 	     (ahbsi.haddr(LINE_HIGH downto LINE_LOW) = LINE_ZERO)))      then	vs.snoop := r.cctrl.dsnoop; -- and hcache;        vs.addr := ahbsi.haddr(TAG_HIGH downto OFFSET_LOW);       end if;      for i in 0 to DSETS-1 loop senable(i) := vs.snoop or rs.snoop; end loop;              readbp := (others => '0');      if (r.xaddress(TAG_HIGH downto OFFSET_LOW) = rs.addr(TAG_HIGH downto OFFSET_LOW)) then rbphit := '1'; end if;          for i in 0 to DSETS-1 loop        if (rs.readbpx(i) and rbphit) = '1' then readbp(i) := '1'; end if;      end loop;              -- clear valid bits on snoop hit (or set hit bits)      for i in DSETS-1 downto 0 loop        if ((rs.snoop and (not mcdo.ba) and not r.flush) = '1')           and ((dcramov.stag(i)(TAG_HIGH downto TAG_LOW) = rs.addr(TAG_HIGH downto TAG_LOW)) or (readbp(i) = '1'))        then          if DSNOOP = 2 then            vh.hit(conv_integer(rs.addr(OFFSET_HIGH downto OFFSET_LOW)))(i) := '1';--             vh.set := std_logic_vector(conv_unsigned(i, SETBITS));          else            snoopaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW);            snoopwe := '1'; snoopset := i;                  end if;        end if;      -- bypass tag data on read/write contention        if (DSNOOP /= 2) and (rs.writebp(i) = '1') then           dcramov.tag(i)(TAG_HIGH downto TAG_LOW) := rs.addr(TAG_HIGH downto TAG_LOW);          dcramov.tag(i)(dlinesize-1 downto 0) := zero32(dlinesize-1 downto 0);        end if;      end loop;