end if;-- generate access parameters during pipeline stall    if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then      taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);    elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')    then      taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);    else      taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);    end if;    if (dci.write or not r.holdn) = '1' then      maddress := r.xaddress(31 downto 0);      read := r.read; size := r.size; edata := dci.maddress;    else      maddress := dci.maddress(31 downto 0);      read := dci.read; size := dci.size; edata := dci.edata;    end if;    newtag := dci.maddress(TAG_HIGH downto TAG_LOW);    vl.waddr := maddress(OFFSET_HIGH downto OFFSET_LOW);  -- lru write address-- generate cache hit and valid bits    if cached /= 0 then hcache := ctbl(conv_integer(dci.maddress(31 downto 28)));    else hcache := '1'; end if;    forcemiss := not dci.asi(3); hit := '0'; set := 0; snoophit := (others => '0');    snoopval := '1';    for i in DSETS-1 downto 0 loop      if DSNOOP = 2 then        snoophit(i) := rh.hit(conv_integer(rh.taddr))(i);      end if;      if (dcramov.tag(i)(TAG_HIGH downto TAG_LOW) = dci.maddress(TAG_HIGH downto TAG_LOW))       then hitv(i) := hcache; end if;       validrawv(i) := hitv(i) and (not r.flush) and (not r.flush2) and (not snoophit(i)) and	genmux(dci.maddress(LINE_HIGH downto LINE_LOW), dcramov.tag(i)(dlinesize-1 downto 0));      validv(i) :=  validrawv(i);      snoopval := snoopval and not snoophit(i);    end loop;    hit := orv(hitv) and not r.flush and not r.flush2; validraw := orv(validrawv);    valid := orv(validv);    if DSETS > 1 then       for i in DSETS-1 downto 0 loop         if (hitv(i) = '1') then	  vset := conv_std_logic_vector(i, SETBITS);        end if;      end loop;      set := conv_integer(vset);      if rlramrd = '1' then set := 1; end if;    else set := 0; end if;    if (dci.dsuen = '1') then diagset := r.xaddress(TAG_LOW+SETBITS-1 downto TAG_LOW);                                                    else diagset := maddress(TAG_LOW + SETBITS - 1 downto TAG_LOW); end if;    case DSETS is    when 1 => ddset := 0;    when 3 => if conv_integer(diagset) < 3 then ddset := conv_integer(diagset); end if;    when others => ddset := conv_integer(diagset);     end case;    if ((r.holdn and dci.enaddr) = '1')  and (r.dstate = "000") then        v.hit := hit; v.xaddress := dci.maddress;	v.read := dci.read; v.size := dci.size;	v.asi := dci.asi(3 downto 0);    end if;-- Store buffer--    wdata := r.wb.data1;    if mcdo.ready = '1' then      v.wb.addr(2) := r.wb.addr(2) or (r.wb.size(0) and r.wb.size(1));      if r.stpend = '1' then        v.stpend := r.req; v.wb.data1 := r.wb.data2; 	v.wb.lock := r.wb.lock and r.req;      end if;    end if;    if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;    if (mcdo.grant and not r.wb.read and r.req) = '1' then v.wb.lock := '0'; end if;        if (dlram = 1) then      if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then        laddr := r.xaddress;      elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0') then        laddr := dci.maddress;      else laddr := dci.eaddress; end if;      if  (dci.enaddr = '1') and (dci.maddress(31 downto 24) = LOCAL_RAM_START)      then lramen := '1'; end if;      if  ((laddr(31 downto 24) = LOCAL_RAM_START)) or ((dci.dsuen = '1') and (dci.asi(4 downto 1) = "0101"))      then lramcs := '1'; end if;          end if;        if (ilram = 1) then       if  (dci.enaddr = '1') and (dci.maddress(31 downto 24) = ILRAM_START)  then ilramen := '1'; end if;    end if;    -- cache freeze operation    if (r.cctrl.ifrz and dci.intack and r.cctrl.ics(0)) = '1' then      v.cctrl.ics := "01";    end if;    if (r.cctrl.dfrz and dci.intack and r.cctrl.dcs(0)) = '1' then      v.cctrl.dcs := "01";    end if;        if r.cctrlwr = '1' then    if (r.xaddress(7 downto 2) = "000000") and (dci.read = '0') then      v.cctrl.dsnoop := dci.maddress(23);      flush        := dci.maddress(22);      iflush       := dci.maddress(21);      v.cctrl.burst:= dci.maddress(16);      v.cctrl.dfrz := dci.maddress(5);      v.cctrl.ifrz := dci.maddress(4);      v.cctrl.dcs  := dci.maddress(3 downto 2);      v.cctrl.ics  := dci.maddress(1 downto 0);                  end if;    end if;    -- main Dcache state machine    case r.dstate is    when "000" =>			-- Idle state      v.nomds := r.nomds and not eholdn;       v.forcemiss := forcemiss; sidle := '1';      if (snoopval = '1') then 	for i in 0 to DSETS-1 loop          v.valid(i) := dcramov.tag(i)(dlinesize-1 downto 0);	end loop;      else v.valid := (others => (others => '0')); end if;      if (r.stpend  = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue	v.wb.addr := dci.maddress; v.wb.size := dci.size; 	v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock;	v.wb.asi := dci.asi(3 downto 0);       end if;      if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify	case dci.asi(4 downto 0) is 	when ASI_SYSR => rdatasel := sysr;		when ASI_DTAG => rdatasel := dtag;	when ASI_DDATA => rdatasel := dddata;	when others =>	end case;      end if;      if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then	case dci.asi(4 downto 0) is 	when ASI_SYSR =>		-- system registers          if (dsu = 0) or (dci.dsuen = '0') then            if (dci.maddress(7 downto 2) = "000000") and (dci.read = '0') then              v.cctrl.dsnoop := dci.edata(23);              flush        := dci.edata(22);              iflush       := dci.edata(21);              v.cctrl.burst:= dci.edata(16);              v.cctrl.dfrz := dci.edata(5);              v.cctrl.ifrz := dci.edata(4);              v.cctrl.dcs  := dci.edata(3 downto 2);              v.cctrl.ics  := dci.edata(1 downto 0);            end if;          else            v.cctrlwr := not dci.read;          end if;	when ASI_ITAG | ASI_IDATA =>		-- Read/write Icache tags	  if ico.flush = '1' then mexc := '1';          else v.dstate := "101"; v.holdn := dci.dsuen; end if;        when ASI_UINST | ASI_SINST =>          if (ilram = 1) then v.dstate := "101"; v.ilramen := '1'; end if; 	when ASI_IFLUSH =>		-- flush instruction cache	  if dci.read = '0' then iflush := '1'; end if; 	when ASI_DFLUSH =>		-- flush data cache	  if dci.read = '0' then flush := '1'; end if; 	when ASI_DDATA =>		-- Read/write Dcache data 	  if (dci.size /= "10") or (r.flush = '1') then -- only word access is allowed 	    mexc := '1'; 	  elsif (dci.read = '0') then 	    dwrite := '1'; ddiagwrite := '1'; 	  end if; 	when ASI_DTAG =>		-- Read/write Dcache tags 	  if (dci.size /= "10") or (r.flush = '1') then -- allow only word access 	    mexc := '1'; 	  elsif (dci.read = '0') then 	    twrite := '1'; tdiagwrite := '1'; 	  end if;	when others =>--          setrepl := std_logic_vector(conv_unsigned(set, SETBITS));	  if dci.read = '1' then	-- read access            if (dlram = 1) and (lramen = '1') then	      lramrd := '1';            elsif (ilram = 1) and (ilramen = '1') then              if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';              else v.dstate := "101"; v.holdn := dci.dsuen; v.ilramen := '1'; end if;              	    elsif dci.dsuen = '0' then              if (not ((r.cctrl.dcs(0) = '1') and ((hit and valid and not forcemiss) = '1')))              then	-- read miss                v.holdn := '0'; v.dstate := "001";                 if ((r.stpend  = '0') or ((mcdo.ready and not r.req) = '1'))                then	-- wait for store queue                  v.req := '1';                   v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);                end if;              else       -- read hit                if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;              end if;            end if;            	  else			-- write access            if (dlram = 1) and (lramen = '1') then              lramwr := '1';	      if (dci.size = "11") then -- double store                v.dstate := "100"; v.xaddress(2) := '1';              end if;             elsif (ilram = 1) and (ilramen = '1') then              if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';              else v.dstate := "101"; v.holdn := dci.dsuen; v.ilramen := '1'; end if;            elsif dci.dsuen = '0' then              if (r.stpend  = '0') or ((mcdo.ready and not r.req)= '1') then	-- wait for store queue                v.req := '1'; v.stpend := '1';                 v.burst := dci.size(1) and dci.size(0);                if (dci.size = "11") then v.dstate := "100"; end if; -- double store              else		-- wait for store queue                v.dstate := "110"; v.holdn := '0';              end if;--	    if (r.cctrl.dcs(0) = '1') and ((hit and (dci.size(1) or validraw)) = '1')               if (r.cctrl.dcs(0) = '1') and (((hit and dci.size(1)) or validraw) = '1')               then  -- write hit                twrite := '1'; dwrite := '1';                if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;                setrepl := conv_std_logic_vector(set, SETBITS);                if DSNOOP /= 0 then                  if ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')                  then v.xaddress := dci.maddress; else v.xaddress := dci.eaddress; end if;                  vs.readbpx(set) := '1';                end if;                                              end if;              if (dci.size = "11") then v.xaddress(2) := '1'; end if;            end if;	  end if;          if (DSETS > 1) then    	    vl.set := conv_std_logic_vector(set, SETBITS);            v.setrepl := conv_std_logic_vector(set, SETBITS);            if ((not hit) and (not r.flush)) = '1' then              case drepl is              when rnd =>                if dsetlock = 1 then                   if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;                  else                    v.setrepl := conv_std_logic_vector(DSETS-1, SETBITS);                    for i in DSETS-1 downto 0 loop                      if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then                        v.setrepl := conv_std_logic_vector(i, SETBITS);                      end if;                    end loop;                  end if;                else                  v.setrepl := r.rndcnt;                end if;              when lru =>                v.setrepl := lru_set(rl.lru(conv_integer(dci.maddress(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to DSETS-1));              when lrr =>                v.setrepl := (others => '0');                if dsetlock = 1 then                   if lock(0) = '1' then v.setrepl(0) := '1';                  else                    v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);                  end if;                else                  v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);                end if;                if v.setrepl(0) = '0' then                  v.lrr := not dcramov.tag(0)(CTAG_LRRPOS);                else                  v.lrr := dcramov.tag(0)(CTAG_LRRPOS);                end if;              end case;            end if;            if (dsetlock = 1) then              if (hit and lock(set)) = '1' then v.lock := '1';              else v.lock := '0'; end if;            end if;                        end if;        end case;      end if;    when "001" => 		-- read miss, wait for memory data      taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);      newtag := r.xaddress(TAG_HIGH downto TAG_LOW);      v.nomds := r.nomds and not eholdn;      v.holdn := v.nomds; rdatasel := memory;      for i in 0 to DSETS-1 loop wlock(i) := r.lock; end loop;      for i in 0 to 3 loop wlrr(i) := r.lrr; end loop;      if r.stpend = '0' then        if mcdo.ready = '1' then          mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';          if (r.cctrl.dcs = "01") then 	    v.hit := mcdo.cache and r.hit; twrite := v.hit;          elsif (r.cctrl.dcs(1) = '1') then 	    v.hit := mcdo.cache and (r.hit or (r.asi(3) and not r.asi(2))); twrite := v.hit;	  end if;           dwrite := twrite; rdatasel := memory;          mexc := mcdo.mexc;	  if r.req = '0' then	    if (((dci.enaddr and not mds) = '1') or               ((dci.eenaddr and mds and eholdn) = '1')) and ((r.cctrl.dcs(0) = '1') or (dlram = 1)) then	      v.dstate := "011"; v.holdn := '0';	    else v.dstate := "000"; end if;	  else v.nomds := '1'; end if;        end if;	v.mexc := mcdo.mexc; v.wb.data2 := mcdo.data;      else	if ((mcdo.ready and not r.req) = '1') then	-- wait for store queue	  v.burst := r.size(1) and r.size(0) and not r.xaddress(2);	  v.wb.addr := r.xaddress; v.wb.size := r.size; 	  v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1'; 	  v.wb.lock := dci.lock; v.wb.asi := r.asi;         end if;      end if;      if DSNOOP /= 0 then vs.readbpx(conv_integer(setrepl)) := '1'; end if;          when "011" =>		-- return from read miss with load pending      taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);      if (dlram = 1) then        laddr := dci.maddress;        if laddr(31 downto 24) = LOCAL_RAM_START then lramcs := '1'; end if;      end if;      v.dstate := "000";     when "100" => 		-- second part of double store cycle      v.dstate := "000";      edata := dci.edata;  -- needed for STD store hit      taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);       if (dlram = 1) and (rlramrd = '1') then	laddr := r.xaddress; lramwr := '1';      else        if (r.cctrl.dcs(0) = '1') and (r.hit = '1') then dwrite := '1'; end if;        v.wb.data2 := dci.edata;       end if;    when "101" =>		-- icache diag and inst local ram access       rdatasel := icache; v.icenable := '1'; v.holdn := dci.dsuen;      if  ico.diagrdy = '1' then	v.dstate := "011"; v.icenable := '0'; mds := not r.read; v.ilramen := '0';      end if;    when "110" => 		-- wait for store buffer to empty (store access)      edata := dci.edata;  -- needed for STD store hit      if ((mcdo.ready and not r.req) = '1') then	-- store queue emptied	if (r.cctrl.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then  -- write hit          taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := '1';	end if;        v.dstate := "000"; 	v.req := '1'; v.burst := r.size(1) and r.size(0); v.stpend := '1';	v.wb.addr := r.xaddress; v.wb.size := r.size;	v.wb.read := r.read; v.wb.data1 := dci.maddress;	v.wb.lock := dci.lock; v.wb.data2 := dci.edata;	v.wb.asi := r.asi; 	if r.size = "11" then v.wb.addr(2) := '0'; end if;      else  -- hold cpu until buffer empty        v.holdn := '0';      end if;    when others => v.dstate := "000";    end case;    if (dlram = 1) then v.lramrd := lramcs; end if; -- read local ram data     -- select data to return on read access-- align if byte/half word read from cache or memory.    if (dsu = 1) and (dci.dsuen = '1') then      v.dsuset := conv_std_logic_vector(ddset, SETBITS);       case dci.asi(4 downto 0) is      when ASI_ITAG | ASI_IDATA =>        v.icenable := not ico.diagrdy;        rdatasel := icache;      when ASI_DTAG =>