-- 庫聲明
library IEEE;
use IEEE.STD_LOGIC_1164.all; 
use WORK.UART_PACKAGE.ALL;
-- 實體聲明
entity detector is
	port (
	clk : in std_logic;
	reset_n : in std_logic;
	RxD : in std_logic;
	new_data : out std_logic );
end detector;

--}} End of automatically maintained section
-- 結構體
architecture detector of detector is

-- 信號監(jiān)測器狀態(tài)機
signal state : dt_state;

begin
	-- enter your statements here --
	-- 主過程
	main : process(reset_n, clk)
	begin
		-- 復位信號
		if reset_n = '0' then
			state <= dt_unlock;
			new_data <= '0';
		elsif rising_edge(clk) then
			-- 檢查輸入信號和狀態(tài)，當輸入為低并且不在鎖定狀態(tài)時，輸出new_data信號 
			if state = dt_unlock and RxD = '0' then
				new_data <= '1';
				state <= dt_lock;
			else
				new_data <= '0';
			end if;
		end if;
			
	end process;

end detector;