# Xilinx CORE Generator 6.1i
# User = 劉韜
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\program\FPGA_PROGRAM\FOR_FPGA\vga_lcd\vga\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=E:\program\FPGA_PROGRAM\FOR_FPGA\vga_lcd\vga
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=E:\program\FPGA_PROGRAM\FOR_FPGA\vga_lcd\vga
SETPROJECT .
Set current Project to E:\program\FPGA_PROGRAM\FOR_FPGA\vga_lcd\vga
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 4375
XIPCPJSENDCORES spartan2e