+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Dec 30 23:22:19 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic
Info: Found 1 design units, including 1 entities, in source file traffic.v
    Info: Found entity 1: traffic
Info: Elaborating entity "traffic" for the top level hierarchy
Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable "ared", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable "ayellow", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable "agreen", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable "aleft", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable "bred", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable "byellow", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable "bleft", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable "bgreen", which holds its previous value in one or more paths through the always construct
Warning (10230): Verilog HDL assignment warning at traffic.v(57): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at traffic.v(59): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at traffic.v(92): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at traffic.v(95): truncated value with size 32 to match size of target (4)
Info (10041): Inferred latch for "bgreen[0]" at traffic.v(20)
Info (10041): Inferred latch for "bgreen[1]" at traffic.v(20)
Info (10041): Inferred latch for "bgreen[2]" at traffic.v(20)
Info (10041): Inferred latch for "bgreen[3]" at traffic.v(20)
Info (10041): Inferred latch for "bgreen[4]" at traffic.v(20)
Info (10041): Inferred latch for "bgreen[5]" at traffic.v(20)
Info (10041): Inferred latch for "bgreen[6]" at traffic.v(20)
Info (10041): Inferred latch for "bgreen[7]" at traffic.v(20)
Info (10041): Inferred latch for "bleft[0]" at traffic.v(20)
Info (10041): Inferred latch for "bleft[1]" at traffic.v(20)
Info (10041): Inferred latch for "bleft[2]" at traffic.v(20)
Info (10041): Inferred latch for "bleft[3]" at traffic.v(20)
Info (10041): Inferred latch for "bleft[4]" at traffic.v(20)
Info (10041): Inferred latch for "bleft[5]" at traffic.v(20)
Info (10041): Inferred latch for "bleft[6]" at traffic.v(20)
Info (10041): Inferred latch for "bleft[7]" at traffic.v(20)
Info (10041): Inferred latch for "byellow[0]" at traffic.v(20)
Info (10041): Inferred latch for "byellow[1]" at traffic.v(20)
Info (10041): Inferred latch for "byellow[2]" at traffic.v(20)
Info (10041): Inferred latch for "byellow[3]" at traffic.v(20)
Info (10041): Inferred latch for "byellow[4]" at traffic.v(20)
Info (10041): Inferred latch for "byellow[5]" at traffic.v(20)
Info (10041): Inferred latch for "byellow[6]" at traffic.v(20)
Info (10041): Inferred latch for "byellow[7]" at traffic.v(20)
Info (10041): Inferred latch for "bred[0]" at traffic.v(20)
Info (10041): Inferred latch for "bred[1]" at traffic.v(20)
Info (10041): Inferred latch for "bred[2]" at traffic.v(20)
Info (10041): Inferred latch for "bred[3]" at traffic.v(20)
Info (10041): Inferred latch for "bred[4]" at traffic.v(20)
Info (10041): Inferred latch for "bred[5]" at traffic.v(20)
Info (10041): Inferred latch for "bred[6]" at traffic.v(20)
Info (10041): Inferred latch for "bred[7]" at traffic.v(20)
Info (10041): Inferred latch for "aleft[0]" at traffic.v(20)
Info (10041): Inferred latch for "aleft[1]" at traffic.v(20)
Info (10041): Inferred latch for "aleft[2]" at traffic.v(20)
Info (10041): Inferred latch for "aleft[3]" at traffic.v(20)
Info (10041): Inferred latch for "aleft[4]" at traffic.v(20)
Info (10041): Inferred latch for "aleft[5]" at traffic.v(20)
Info (10041): Inferred latch for "aleft[6]" at traffic.v(20)
Info (10041): Inferred latch for "aleft[7]" at traffic.v(20)
Info (10041): Inferred latch for "agreen[0]" at traffic.v(20)
Info (10041): Inferred latch for "agreen[1]" at traffic.v(20)
Info (10041): Inferred latch for "agreen[2]" at traffic.v(20)
Info (10041): Inferred latch for "agreen[3]" at traffic.v(20)
Info (10041): Inferred latch for "agreen[4]" at traffic.v(20)
Info (10041): Inferred latch for "agreen[5]" at traffic.v(20)
Info (10041): Inferred latch for "agreen[6]" at traffic.v(20)
Info (10041): Inferred latch for "agreen[7]" at traffic.v(20)
Info (10041): Inferred latch for "ayellow[0]" at traffic.v(20)
Info (10041): Inferred latch for "ayellow[1]" at traffic.v(20)
Info (10041): Inferred latch for "ayellow[2]" at traffic.v(20)
Info (10041): Inferred latch for "ayellow[3]" at traffic.v(20)
Info (10041): Inferred latch for "ayellow[4]" at traffic.v(20)
Info (10041): Inferred latch for "ayellow[5]" at traffic.v(20)
Info (10041): Inferred latch for "ayellow[6]" at traffic.v(20)
Info (10041): Inferred latch for "ayellow[7]" at traffic.v(20)
Info (10041): Inferred latch for "ared[0]" at traffic.v(20)
Info (10041): Inferred latch for "ared[1]" at traffic.v(20)
Info (10041): Inferred latch for "ared[2]" at traffic.v(20)
Info (10041): Inferred latch for "ared[3]" at traffic.v(20)
Info (10041): Inferred latch for "ared[4]" at traffic.v(20)
Info (10041): Inferred latch for "ared[5]" at traffic.v(20)
Info (10041): Inferred latch for "ared[6]" at traffic.v(20)
Info (10041): Inferred latch for "ared[7]" at traffic.v(20)
Info: State machine "|traffic|countb" contains 5 states
Info: State machine "|traffic|counta" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|traffic|countb"
Info: Encoding result for state machine "|traffic|countb"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "countb.011"
        Info: Encoded state bit "countb.010"
        Info: Encoded state bit "countb.001"
        Info: Encoded state bit "countb.000"
        Info: Encoded state bit "countb.100"
    Info: State "|traffic|countb.000" uses code string "00000"
    Info: State "|traffic|countb.001" uses code string "00110"
    Info: State "|traffic|countb.010" uses code string "01010"
    Info: State "|traffic|countb.011" uses code string "10010"
    Info: State "|traffic|countb.100" uses code string "00011"
Info: Selected Auto state machine encoding method for state machine "|traffic|counta"
Info: Encoding result for state machine "|traffic|counta"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "counta.011"
        Info: Encoded state bit "counta.010"
        Info: Encoded state bit "counta.001"
        Info: Encoded state bit "counta.000"
        Info: Encoded state bit "counta.100"
    Info: State "|traffic|counta.000" uses code string "00000"
    Info: State "|traffic|counta.001" uses code string "00110"
    Info: State "|traffic|counta.010" uses code string "01010"
    Info: State "|traffic|counta.011" uses code string "10010"
    Info: State "|traffic|counta.100" uses code string "00011"
Info: Duplicate registers merged to single register
    Info: Duplicate register "counta.011" merged to single register "LAMPA[0]~reg0"
    Info: Duplicate register "counta.001" merged to single register "LAMPA[1]~reg0"
Info: Duplicate registers merged to single register
    Info: Duplicate register "counta.000" merged to single register "LAMPA[3]~reg0", power-up level changed
Info: 4 registers lost all their fanouts during netlist optimizations. The first 4 are displayed below.
    Info: Register "countb~37" lost all its fanouts during netlist optimizations.
    Info: Register "countb~38" lost all its fanouts during netlist optimizations.
    Info: Register "counta~37" lost all its fanouts during netlist optimizations.
    Info: Register "counta~38" lost all its fanouts during netlist optimizations.
Info: Implemented 93 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 24 output pins
    Info: Implemented 67 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Allocated 141 megabytes of memory during processing
    Info: Processing ended: Tue Dec 30 23:22:22 2008
    Info: Elapsed time: 00:00:03