# !COUNT0 &  COUNT2;

-- Node name is ':18' = 'COUNT3' 
-- Equation name is 'COUNT3', location is LC1_C32, type is buried.
COUNT3   = DFFE( _EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  COUNT0 &  COUNT1 &  COUNT2 & !COUNT3
         #  COUNT1 & !COUNT2 &  COUNT3
         #  COUNT0 & !COUNT2 &  COUNT3
         # !COUNT1 &  COUNT2 &  COUNT3
         #  COUNT0 & !COUNT1 &  COUNT3
         # !COUNT0 &  COUNT1 &  COUNT3
         # !COUNT0 &  COUNT2 &  COUNT3;

-- Node name is 'data0' 
-- Equation name is 'data0', type is output 
data0    =  GND;

-- Node name is 'data1' 
-- Equation name is 'data1', type is output 
data1    =  _LC6_C32;

-- Node name is 'data2' 
-- Equation name is 'data2', type is output 
data2    = !_LC2_C25;

-- Node name is 'data3' 
-- Equation name is 'data3', type is output 
data3    =  VCC;

-- Node name is 'data4' 
-- Equation name is 'data4', type is output 
data4    =  _LC6_C25;

-- Node name is 'data5' 
-- Equation name is 'data5', type is output 
data5    =  _LC4_C32;

-- Node name is 'data6' 
-- Equation name is 'data6', type is output 
data6    =  _LC7_C25;

-- Node name is 'data7' 
-- Equation name is 'data7', type is output 
data7    =  _LC3_C19;

-- Node name is ':201' 
-- Equation name is '_LC7_C32', type is buried 
_LC7_C32 = LCELL( _EQ005);
  _EQ005 = !COUNT1 &  COUNT2 & !COUNT3
         #  COUNT0 &  COUNT2 & !COUNT3;

-- Node name is ':210' 
-- Equation name is '_LC2_C25', type is buried 
!_LC2_C25 = _LC2_C25~NOT;
_LC2_C25~NOT = LCELL( _EQ006);
  _EQ006 = !COUNT1
         # !COUNT0
         #  COUNT2
         #  COUNT3;

-- Node name is ':222' 
-- Equation name is '_LC5_C32', type is buried 
!_LC5_C32 = _LC5_C32~NOT;
_LC5_C32~NOT = LCELL( _EQ007);
  _EQ007 =  COUNT0
         #  COUNT3
         # !COUNT1
         #  COUNT2;

-- Node name is ':246' 
-- Equation name is '_LC3_C25', type is buried 
!_LC3_C25 = _LC3_C25~NOT;
_LC3_C25~NOT = LCELL( _EQ008);
  _EQ008 =  COUNT1
         #  COUNT2
         #  COUNT0
         #  COUNT3;

-- Node name is ':249' 
-- Equation name is '_LC3_C19', type is buried 
_LC3_C19 = LCELL( _EQ009);
  _EQ009 = !COUNT1 &  COUNT2 & !COUNT3
         #  COUNT0 &  COUNT2 & !COUNT3
         # !COUNT0 & !COUNT2 & !COUNT3;

-- Node name is ':269' 
-- Equation name is '_LC8_C25', type is buried 
_LC8_C25 = LCELL( _EQ010);
  _EQ010 =  COUNT1 &  COUNT2 & !COUNT3;

-- Node name is ':276' 
-- Equation name is '_LC7_C25', type is buried 
_LC7_C25 = LCELL( _EQ011);
  _EQ011 = !_LC1_C25 &  _LC8_C25
         # !_LC1_C25 &  _LC2_C25
         #  _LC3_C25;

-- Node name is ':294' 
-- Equation name is '_LC3_C32', type is buried 
_LC3_C32 = LCELL( _EQ012);
  _EQ012 =  COUNT0 &  COUNT1 & !COUNT2 & !COUNT3
         # !COUNT0 &  COUNT1 &  COUNT2 & !COUNT3;

-- Node name is ':303' 
-- Equation name is '_LC4_C32', type is buried 
_LC4_C32 = LCELL( _EQ013);
  _EQ013 =  _LC3_C32 & !_LC5_C32
         #  _LC2_C32;

-- Node name is '~327~1' 
-- Equation name is '~327~1', location is LC1_C25, type is buried.
-- synthesized logic cell 
_LC1_C25 = LCELL( _EQ014);
  _EQ014 = !COUNT0 &  COUNT1 & !COUNT2 & !COUNT3
         #  COUNT0 & !COUNT1 & !COUNT2 & !COUNT3;

-- Node name is '~327~2' 
-- Equation name is '~327~2', location is LC4_C25, type is buried.
-- synthesized logic cell 
_LC4_C25 = LCELL( _EQ015);
  _EQ015 =  COUNT3
         # !COUNT2
         # !COUNT0 & !COUNT1;

-- Node name is ':332' 
-- Equation name is '_LC6_C25', type is buried 
_LC6_C25 = LCELL( _EQ016);
  _EQ016 =  _LC1_C25 & !_LC3_C25
         # !_LC3_C25 &  _LC4_C25
         #  _LC2_C25 & !_LC3_C25;

-- Node name is '~411~1' 
-- Equation name is '~411~1', location is LC2_C32, type is buried.
-- synthesized logic cell 
_LC2_C32 = LCELL( _EQ017);
  _EQ017 = !COUNT1 & !COUNT2 & !COUNT3;

-- Node name is ':411' 
-- Equation name is '_LC6_C32', type is buried 
_LC6_C32 = LCELL( _EQ018);
  _EQ018 =  _LC2_C32
         #  _LC3_C32 & !_LC5_C32
         # !_LC5_C32 &  _LC7_C32;



Project Information                           g:\pldshiyan\alpher2\alpher2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:08


Memory Allocated
-----------------

Peak memory allocated during compilation  = 24,499K