library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jiandan is
port(clk1: in std_logic;
    reset: in std_logic;
     pout: out std_logic_vector(12 downto 1));
end jiandan;
architecture traffic of jiandan is
signal er,ey,eg: std_logic;
signal sr,sy,sg: std_logic;
signal wr,wy,wg: std_logic;
signal nr,ny,ng: std_logic;
signal count: integer range 0 to 11;
signal state: integer range 0 to 4;
begin
process(clk1,reset,count)
begin
if reset='1' then
count<=0;
state<=0;
else
if(clk1' event and clk1='1') then
count<=count+1;
if(count=11) then
state<=state+1;
end if;
if(state>4) then 
state<=0;
count<=0;
end if;
end if;
end if;
case state is
when 0=>ey<='1'; wy<='1'; sy<='1'; ny<='1';
        eg<='0'; wg<='0'; sg<='0'; ng<='0';
        er<='0'; wr<='0'; sr<='0'; nr<='0';

when 1=>ey<='0'; wy<='0'; sy<='0'; ny<='0';
        eg<='1'; wg<='1'; sg<='0'; ng<='0';
        er<='0'; wr<='0'; sr<='1'; nr<='1';

when 2=>ey<='1'; wy<='1'; sy<='0'; ny<='0';
        eg<='1'; wg<='1'; sg<='0'; ng<='0';
        er<='0'; wr<='0'; sr<='1'; nr<='1';

when 3=>ey<='0'; wy<='0'; sy<='0'; ny<='0';
        eg<='0'; wg<='0'; sg<='1'; ng<='1';
        er<='1'; wr<='1'; sr<='0'; nr<='0';

when 4=>ey<='0'; wy<='0'; sy<='1'; ny<='1';
        eg<='0'; wg<='0'; sg<='1'; ng<='1';
        er<='1'; wr<='1'; sr<='0'; nr<='0';
when others=>null;
end case;
end process;
pout(1)<=er; pout(2)<=eg; pout(3)<=ey;
pout(4)<=sr; pout(5)<=sg; pout(6)<=sy;
pout(7)<=wr; pout(8)<=wg; pout(9)<=wy;
pout(10)<=nr; pout(11)<=ng; pout(12)<=ny;
end traffic;