library ieee;
use ieee.std_logic_1164.all;
entity load_n is
port(
	mux_out: out std_logic_vector(8 downto 0);
	mux_0:in std_logic_vector(8 downto 0);
	mux_1:in std_logic_vector(8 downto 0);
	load:in std_logic);
end load_n;
architecture behav of load_n is
begin
 process(load,mux_0,mux_1)
  begin
 
  case load is
	when '0'=>mux_out<=mux_0;
	when '1'=>mux_out<=mux_1;
	when others=>null;	
  end case;	
 end process;
end behav;