Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Fri Jun 27 09:26:49 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dividend4 -c dividend4
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "state_graph:u5|srg4:u1|srg_4[0]" as buffer
    Info: Detected ripple clock "state_graph:u5|srg4:u1|srg_4[2]" as buffer
    Info: Detected ripple clock "state_graph:u5|srg4:u1|srg_4[1]" as buffer
Info: Clock "clk" has Internal fmax of 39.06 MHz between source register "shift:u4|shiftin[1]" and destination register "quotient[1]~reg0" (period= 25.6 ns)
    Info: + Longest register to register delay is 4.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC18; Fanout = 2; REG Node = 'shift:u4|shiftin[1]'
        Info: 2: + IC(1.500 ns) + CELL(3.000 ns) = 4.500 ns; Loc. = LC35; Fanout = 1; REG Node = 'quotient[1]~reg0'
        Info: Total cell delay = 3.000 ns ( 66.67 % )
        Info: Total interconnect delay = 1.500 ns ( 33.33 % )
    Info: - Smallest clock skew is -5.900 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.200 ns
            Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC35; Fanout = 1; REG Node = 'quotient[1]~reg0'
            Info: Total cell delay = 2.200 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 8.100 ns
            Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC34; Fanout = 9; REG Node = 'state_graph:u5|srg4:u1|srg_4[0]'
            Info: 3: + IC(1.400 ns) + CELL(3.100 ns) = 8.100 ns; Loc. = LC18; Fanout = 2; REG Node = 'shift:u4|shiftin[1]'
            Info: Total cell delay = 6.700 ns ( 82.72 % )
            Info: Total interconnect delay = 1.400 ns ( 17.28 % )
    Info: + Micro clock to output delay of source is 1.400 ns
    Info: + Micro setup delay of destination is 1.000 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "state_graph:u5|load" and destination pin or register "shift:u4|shiftin[8]" for clock "clk" (Hold time is 1.7 ns)
    Info: + Largest clock skew is 5.900 ns
        Info: + Longest clock path from clock "clk" to destination register is 8.100 ns
            Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC34; Fanout = 9; REG Node = 'state_graph:u5|srg4:u1|srg_4[0]'
            Info: 3: + IC(1.400 ns) + CELL(3.100 ns) = 8.100 ns; Loc. = LC32; Fanout = 4; REG Node = 'shift:u4|shiftin[8]'
            Info: Total cell delay = 6.700 ns ( 82.72 % )
            Info: Total interconnect delay = 1.400 ns ( 17.28 % )
        Info: - Shortest clock path from clock "clk" to source register is 2.200 ns
            Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC10; Fanout = 34; REG Node = 'state_graph:u5|load'
            Info: Total cell delay = 2.200 ns ( 100.00 % )
    Info: - Micro clock to output delay of source is 1.400 ns
    Info: - Shortest register to register delay is 4.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 34; REG Node = 'state_graph:u5|load'
        Info: 2: + IC(1.500 ns) + CELL(3.000 ns) = 4.500 ns; Loc. = LC32; Fanout = 4; REG Node = 'shift:u4|shiftin[8]'
        Info: Total cell delay = 3.000 ns ( 66.67 % )
        Info: Total interconnect delay = 1.500 ns ( 33.33 % )
    Info: + Micro hold delay of destination is 1.700 ns
Info: tsu for register "state_graph:u5|input" (data pin = "st", clock pin = "clk") is 3.400 ns
    Info: + Longest pin to register delay is 4.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_79; Fanout = 3; PIN Node = 'st'
        Info: 2: + IC(1.400 ns) + CELL(3.000 ns) = 4.600 ns; Loc. = LC13; Fanout = 2; REG Node = 'state_graph:u5|input'
        Info: Total cell delay = 3.200 ns ( 69.57 % )
        Info: Total interconnect delay = 1.400 ns ( 30.43 % )
    Info: + Micro setup delay of destination is 1.000 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.200 ns
        Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC13; Fanout = 2; REG Node = 'state_graph:u5|input'
        Info: Total cell delay = 2.200 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "quotient[0]" through register "quotient[0]~en" is 9.700 ns
    Info: + Longest clock path from clock "clk" to source register is 2.200 ns
        Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC43; Fanout = 8; REG Node = 'quotient[0]~en'
        Info: Total cell delay = 2.200 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.400 ns
    Info: + Longest register to pin delay is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC43; Fanout = 8; REG Node = 'quotient[0]~en'
        Info: 2: + IC(1.400 ns) + CELL(4.700 ns) = 6.100 ns; Loc. = PIN_18; Fanout = 0; PIN Node = 'quotient[0]'
        Info: Total cell delay = 4.700 ns ( 77.05 % )
        Info: Total interconnect delay = 1.400 ns ( 22.95 % )
Info: th for register "sub_5:u3|differin[3]" (data pin = "divisor[1]", clock pin = "clk") is 5.300 ns
    Info: + Longest clock path from clock "clk" to destination register is 8.200 ns
        Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC7; Fanout = 16; REG Node = 'state_graph:u5|srg4:u1|srg_4[1]'
        Info: 3: + IC(1.500 ns) + CELL(3.100 ns) = 8.200 ns; Loc. = LC6; Fanout = 2; REG Node = 'sub_5:u3|differin[3]'
        Info: Total cell delay = 6.700 ns ( 81.71 % )
        Info: Total interconnect delay = 1.500 ns ( 18.29 % )
    Info: + Micro hold delay of destination is 1.700 ns
    Info: - Shortest pin to register delay is 4.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_6; Fanout = 15; PIN Node = 'divisor[1]'
        Info: 2: + IC(1.400 ns) + CELL(3.000 ns) = 4.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'sub_5:u3|differin[3]'
        Info: Total cell delay = 3.200 ns ( 69.57 % )
        Info: Total interconnect delay = 1.400 ns ( 30.43 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Allocated 110 megabytes of memory during processing
    Info: Processing ended: Fri Jun 27 09:26:50 2008
    Info: Elapsed time: 00:00:01