library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dividend4 is
port(dividend_in:in std_logic_vector(7 downto 0);
	divisor:in std_logic_vector(3 downto 0);
	clk:in std_logic;
	st:in std_logic;
	quotient:out std_logic_vector(3 downto 0);
	remainder:out std_logic_vector(3 downto 0);
	overflow:out std_logic);
end dividend4;
architecture behavioral of dividend4 is
  signal x:std_logic_vector(8 downto 0);
  signal shift_load:std_logic_vector(8 downto 0);
  signal c:std_logic;
  signal load:std_logic;
  signal subout:std_logic_vector(4 downto 0);
  signal isover:std_logic;
  signal diag:std_logic;
  signal su_en:std_logic;
  signal sh_en:std_logic:='0';
  component state_graph
	port(
	st:in std_logic;
	clk:in std_logic;
	overflow:out std_logic;
	load:out std_logic;
	c:in std_logic;
	diag,su_en:out std_logic;
	sh_en:out std_logic;
	isover:out std_logic);
end component;
component diag_c
	port(comp1:in std_logic_vector(4 downto 0);
		comp2:in std_logic_vector(4 downto 0);
		diag:in std_logic;
		c:out std_logic);
end component;	
	
 component sub_5
  port(minuend:in std_logic_vector(4 downto 0);
		subtrahend:in std_logic_vector(4 downto 0);
		su_en:in std_logic;
		c:in std_logic;
		differ:out std_logic_vector(4 downto 0));
  end component;
component shift
	port(shifted:in std_logic_vector(8 downto 0);
		sh_en:in std_logic;
		load:in std_logic;
		c:in std_logic;
		differ:out std_logic_vector(8 downto 0));
end component;
  component load_n
	port(mux_out:out std_logic_vector(8 downto 0);
		mux_0:in std_logic_vector(8 downto 0);
		mux_1:in std_logic_vector(8 downto 0);
		load:in std_logic);
	end component;
begin
	u1:load_n port map(mux_out=>shift_load,mux_0=>subout&x(3 downto 0),mux_1=>'0'&dividend_in,load=>load);
	u2:diag_c port map(x(8 downto 4),'0'&divisor,diag,c);
	u3:sub_5 port map(x(8 downto 4),'0'&divisor,su_en,c,subout);
	u4:shift port map(shift_load,sh_en,load,c,x);
	u5:state_graph port map(st,clk,overflow,load,c,diag,su_en,sh_en,isover);
	process(subout,isover,x)
	begin
	if (clk'event and clk='0') then
	if isover='1' then remainder<=subout(3 downto 0);quotient<=x(3 downto 0);else remainder<="ZZZZ";quotient<="ZZZZ";
	end if;
	end if;
	end process;
	end behavioral;