?? altfp_div0.vhd
字號:
-- megafunction wizard: %ALTFP_DIV%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_div
-- ============================================================
-- File Name: altfp_div0.vhd
-- Megafunction Name(s):
-- altfp_div
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 7.2 Build 151 09/26/2007 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2007 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_div CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Stratix" EXCEPTION_HANDLING="YES" OPTIMIZE="AREA" PIPELINE=33 REDUCED_FUNCTIONALITY="YES" WIDTH_EXP=8 WIDTH_MAN=23 clock dataa datab division_by_zero nan overflow result underflow
--VERSION_BEGIN 7.2 cbx_altbarrel_shift 2007:06:21:18:04:30:SJ cbx_altfp_div 2007:07:16:18:07:06:SJ cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ VERSION_END
--altfp_div_srt_ext CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix" ITERATION=14 OPTMIZE="AREA" WIDTH_DIV=24 aclr clken clock denom numer quotient
--VERSION_BEGIN 7.2 cbx_altbarrel_shift 2007:06:21:18:04:30:SJ cbx_altfp_div 2007:07:16:18:07:06:SJ cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ VERSION_END
--srt_block_int CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix" OPTIMIZE="AREA" POSITION="MIDDLE" WIDTH_DIV=24 WIDTH_RK_IN=25 WIDTH_RK_OUT=25 WIDTH_ROM=3 WIDTH_ROM_ADD=12 aclr clken clock divider divider_reg Rk Rk_next rom
--VERSION_BEGIN 7.2 cbx_altbarrel_shift 2007:06:21:18:04:30:SJ cbx_altfp_div 2007:07:16:18:07:06:SJ cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ VERSION_END
--qds_block CBX_AUTO_BLACKBOX="ALL" aclr clken clock decoder_bus decoder_output
--VERSION_BEGIN 7.2 cbx_altbarrel_shift 2007:06:21:18:04:30:SJ cbx_altfp_div 2007:07:16:18:07:06:SJ cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ VERSION_END
LIBRARY lpm;
USE lpm.lpm_components.all;
--synthesis_resources = lpm_compare 4 lpm_mux 1 lut 3
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altfp_div0_qds_block_6a7 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
decoder_bus : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
decoder_output : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END altfp_div0_qds_block_6a7;
ARCHITECTURE RTL OF altfp_div0_qds_block_6a7 IS
ATTRIBUTE synthesis_clearbox : boolean;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL q_next_dffe : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_cmpr36_aleb : STD_LOGIC;
SIGNAL wire_cmpr37_aleb : STD_LOGIC;
SIGNAL wire_cmpr38_aleb : STD_LOGIC;
SIGNAL wire_cmpr39_aleb : STD_LOGIC;
SIGNAL wire_mux35_data_2d : STD_LOGIC_2D(15 DOWNTO 0, 31 DOWNTO 0);
SIGNAL wire_mux35_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_qds_block30_w_lg_w_k_comp_w_range1601w1611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block30_w_lg_w_k_comp_w_range1603w1613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block30_w_lg_w_k_comp_w_range1599w1610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block30_w_lg_w_k_comp_w_range1602w1612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block30_w_lg_w_k_comp_w_range1603w1607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block30_w_lg_w_lg_w_k_comp_w_range1603w1613w1614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block30_w_lg_w_lg_w_k_comp_w_range1603w1607w1608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL decoder_output_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL Div_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL k_comp_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL mk_bus_const_w : STD_LOGIC_VECTOR (511 DOWNTO 0);
SIGNAL mk_bus_w : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL mk_neg1_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL mk_pos0_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL mk_pos1_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL mk_pos2_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL q_next_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL Rk_in_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL Rk_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_qds_block30_w_k_comp_w_range1599w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block30_w_k_comp_w_range1601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block30_w_k_comp_w_range1602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block30_w_k_comp_w_range1603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_qds_block30_w_lg_w_k_comp_w_range1601w1611w(0) <= wire_qds_block30_w_k_comp_w_range1601w(0) AND wire_qds_block30_w_lg_w_k_comp_w_range1599w1610w(0);
wire_qds_block30_w_lg_w_k_comp_w_range1603w1613w(0) <= wire_qds_block30_w_k_comp_w_range1603w(0) AND wire_qds_block30_w_lg_w_k_comp_w_range1602w1612w(0);
wire_qds_block30_w_lg_w_k_comp_w_range1599w1610w(0) <= NOT wire_qds_block30_w_k_comp_w_range1599w(0);
wire_qds_block30_w_lg_w_k_comp_w_range1602w1612w(0) <= NOT wire_qds_block30_w_k_comp_w_range1602w(0);
wire_qds_block30_w_lg_w_k_comp_w_range1603w1607w(0) <= NOT wire_qds_block30_w_k_comp_w_range1603w(0);
wire_qds_block30_w_lg_w_lg_w_k_comp_w_range1603w1613w1614w(0) <= wire_qds_block30_w_lg_w_k_comp_w_range1603w1613w(0) OR wire_qds_block30_w_lg_w_k_comp_w_range1601w1611w(0);
wire_qds_block30_w_lg_w_lg_w_k_comp_w_range1603w1607w1608w(0) <= wire_qds_block30_w_lg_w_k_comp_w_range1603w1607w(0) OR wire_qds_block30_w_k_comp_w_range1599w(0);
decoder_output <= decoder_output_w;
decoder_output_w <= q_next_dffe;
Div_w <= decoder_bus(3 DOWNTO 0);
k_comp_w <= ( wire_cmpr39_aleb & wire_cmpr38_aleb & wire_cmpr37_aleb & wire_cmpr36_aleb);
mk_bus_const_w <= ( "01011101000111111110000110100011" & "01011010000111101110001010100110" & "01010111000111011110001110101001" & "01010100000111001110010010101100" & "01010001000110111110010110101111" & "01001110000110101110011010110010" & "01001011000110011110011110110101" & "01001000000110001110100010111000" & "01000101000101111110100110111011" & "01000010000101101110101010111110" & "00111111000101011110101111000001" & "00111100000101001110110011000100" & "00111001000100111110110111000111" & "00110110000100101110111011001010" & "00110011000100011110111111001101" & "00110000000100001111000011010000");
mk_bus_w <= wire_mux35_result;
mk_neg1_w <= ( mk_bus_w(7) & mk_bus_w(7 DOWNTO 0));
mk_pos0_w <= ( mk_bus_w(15) & mk_bus_w(15 DOWNTO 8));
mk_pos1_w <= ( mk_bus_w(23) & mk_bus_w(23 DOWNTO 16));
mk_pos2_w <= ( mk_bus_w(31) & mk_bus_w(31 DOWNTO 24));
q_next_w <= ( k_comp_w(1) & wire_qds_block30_w_lg_w_lg_w_k_comp_w_range1603w1607w1608w & wire_qds_block30_w_lg_w_lg_w_k_comp_w_range1603w1613w1614w);
Rk_in_w <= ( decoder_bus(11 DOWNTO 4) & "0");
Rk_w <= Rk_in_w;
wire_qds_block30_w_k_comp_w_range1599w(0) <= k_comp_w(0);
wire_qds_block30_w_k_comp_w_range1601w(0) <= k_comp_w(1);
wire_qds_block30_w_k_comp_w_range1602w(0) <= k_comp_w(2);
wire_qds_block30_w_k_comp_w_range1603w(0) <= k_comp_w(3);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN q_next_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN q_next_dffe <= q_next_w;
END IF;
END IF;
END PROCESS;
cmpr36 : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aleb => wire_cmpr36_aleb,
dataa => Rk_w,
datab => mk_neg1_w
);
cmpr37 : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aleb => wire_cmpr37_aleb,
dataa => Rk_w,
datab => mk_pos0_w
);
cmpr38 : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aleb => wire_cmpr38_aleb,
dataa => Rk_w,
datab => mk_pos1_w
);
cmpr39 : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aleb => wire_cmpr39_aleb,
dataa => Rk_w,
datab => mk_pos2_w
);
loop7 : FOR i IN 0 TO 15 GENERATE
loop8 : FOR j IN 0 TO 31 GENERATE
wire_mux35_data_2d(i, j) <= mk_bus_const_w(i*32+j);
END GENERATE loop8;
END GENERATE loop7;
mux35 : lpm_mux
GENERIC MAP (
LPM_SIZE => 16,
LPM_WIDTH => 32,
LPM_WIDTHS => 4
)
PORT MAP (
data => wire_mux35_data_2d,
result => wire_mux35_result,
sel => Div_w
);
END RTL; --altfp_div0_qds_block_6a7
LIBRARY lpm;
USE lpm.lpm_components.all;
--synthesis_resources = lpm_add_sub 3 lpm_compare 4 lpm_mux 2 lut 102
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altfp_div0_srt_block_int_27k IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
divider : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
divider_reg : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
Rk : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
Rk_next : OUT STD_LOGIC_VECTOR (24 DOWNTO 0);
rom : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END altfp_div0_srt_block_int_27k;
ARCHITECTURE RTL OF altfp_div0_srt_block_int_27k IS
ATTRIBUTE synthesis_clearbox : boolean;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL divider_dffe : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL divider_dffe_1a : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL Rk_dffe : STD_LOGIC_VECTOR(24 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL Rk_next_dffe : STD_LOGIC_VECTOR(24 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL rom_out_dffe : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_add_sub32_w_lg_w_lg_cout1532w1533w : STD_LOGIC_VECTOR (10 DOWNTO 0);
SIGNAL wire_add_sub32_w_lg_cout1530w : STD_LOGIC_VECTOR (10 DOWNTO 0);
SIGNAL wire_add_sub32_w_lg_cout1532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub32_w_lg_w_lg_w_lg_cout1532w1533w1534w : STD_LOGIC_VECTOR (10 DOWNTO 0);
SIGNAL wire_add_sub32_cout : STD_LOGIC;
SIGNAL wire_add_sub32_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_add_sub33_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_add_sub33_w_result_range1531w : STD_LOGIC_VECTOR (10 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_add_sub34_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_add_sub34_w_result_range1529w : STD_LOGIC_VECTOR (10 DOWNTO 0);
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