{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 27 09:22:45 2008 " "Info: Processing started: Fri Jun 27 09:22:45 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dividend4 -c dividend4 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dividend4 -c dividend4" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dividend4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dividend4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dividend4-behavioral " "Info: Found design unit 1: dividend4-behavioral" {  } { { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 dividend4 " "Info: Found entity 1: dividend4" {  } { { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "load_n.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file load_n.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 load_n-behav " "Info: Found design unit 1: load_n-behav" {  } { { "load_n.vhd" "" { Text "D:/altera/myproject/dividend4/load_n.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 load_n " "Info: Found entity 1: load_n" {  } { { "load_n.vhd" "" { Text "D:/altera/myproject/dividend4/load_n.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sub_5.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sub_5.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sub_5-behav " "Info: Found design unit 1: sub_5-behav" {  } { { "sub_5.vhd" "" { Text "D:/altera/myproject/dividend4/sub_5.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sub_5 " "Info: Found entity 1: sub_5" {  } { { "sub_5.vhd" "" { Text "D:/altera/myproject/dividend4/sub_5.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "state_graph.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file state_graph.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 state_graph-behavioral " "Info: Found design unit 1: state_graph-behavioral" {  } { { "state_graph.vhd" "" { Text "D:/altera/myproject/dividend4/state_graph.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 state_graph " "Info: Found entity 1: state_graph" {  } { { "state_graph.vhd" "" { Text "D:/altera/myproject/dividend4/state_graph.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "srg4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file srg4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 srg4-behav " "Info: Found design unit 1: srg4-behav" {  } { { "srg4.vhd" "" { Text "D:/altera/myproject/dividend4/srg4.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 srg4 " "Info: Found entity 1: srg4" {  } { { "srg4.vhd" "" { Text "D:/altera/myproject/dividend4/srg4.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shift.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file shift.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shift-behav " "Info: Found design unit 1: shift-behav" {  } { { "shift.vhd" "" { Text "D:/altera/myproject/dividend4/shift.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 shift " "Info: Found entity 1: shift" {  } { { "shift.vhd" "" { Text "D:/altera/myproject/dividend4/shift.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "diag_c.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file diag_c.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 diag_c-behav " "Info: Found design unit 1: diag_c-behav" {  } { { "diag_c.vhd" "" { Text "D:/altera/myproject/dividend4/diag_c.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 diag_c " "Info: Found entity 1: diag_c" {  } { { "diag_c.vhd" "" { Text "D:/altera/myproject/dividend4/diag_c.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "get_res.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file get_res.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 get_res-behav " "Info: Found design unit 1: get_res-behav" {  } { { "get_res.vhd" "" { Text "D:/altera/myproject/dividend4/get_res.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 get_res " "Info: Found entity 1: get_res" {  } { { "get_res.vhd" "" { Text "D:/altera/myproject/dividend4/get_res.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dividend4 " "Info: Elaborating entity \"dividend4\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk dividend4.vhd(70) " "Warning (10492): VHDL Process Statement warning at dividend4.vhd(70): signal \"clk\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 70 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "load_n load_n:u1 " "Info: Elaborating entity \"load_n\" for hierarchy \"load_n:u1\"" {  } { { "dividend4.vhd" "u1" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 63 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "diag_c diag_c:u2 " "Info: Elaborating entity \"diag_c\" for hierarchy \"diag_c:u2\"" {  } { { "dividend4.vhd" "u2" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 64 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub_5 sub_5:u3 " "Info: Elaborating entity \"sub_5\" for hierarchy \"sub_5:u3\"" {  } { { "dividend4.vhd" "u3" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 65 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}