?? prev_cmp_dividend4.tan.qmsg
字號:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 8 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "state_graph:u5\|srg4:u1\|srg_4\[0\] " "Info: Detected ripple clock \"state_graph:u5\|srg4:u1\|srg_4\[0\]\" as buffer" { } { { "srg4.vhd" "" { Text "D:/altera/myproject/dividend4/srg4.vhd" 13 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "state_graph:u5\|srg4:u1\|srg_4\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "state_graph:u5\|srg4:u1\|srg_4\[2\] " "Info: Detected ripple clock \"state_graph:u5\|srg4:u1\|srg_4\[2\]\" as buffer" { } { { "srg4.vhd" "" { Text "D:/altera/myproject/dividend4/srg4.vhd" 13 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "state_graph:u5\|srg4:u1\|srg_4\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "state_graph:u5\|srg4:u1\|srg_4\[1\] " "Info: Detected ripple clock \"state_graph:u5\|srg4:u1\|srg_4\[1\]\" as buffer" { } { { "srg4.vhd" "" { Text "D:/altera/myproject/dividend4/srg4.vhd" 13 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "state_graph:u5\|srg4:u1\|srg_4\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register shift:u4\|shiftin\[1\] register quotient\[1\]~reg0 38.76 MHz 25.8 ns Internal " "Info: Clock \"clk\" has Internal fmax of 38.76 MHz between source register \"shift:u4\|shiftin\[1\]\" and destination register \"quotient\[1\]~reg0\" (period= 25.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.500 ns + Longest register register " "Info: + Longest register to register delay is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shift:u4\|shiftin\[1\] 1 REG LC20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC20; Fanout = 2; REG Node = 'shift:u4\|shiftin\[1\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { shift:u4|shiftin[1] } "NODE_NAME" } } { "shift.vhd" "" { Text "D:/altera/myproject/dividend4/shift.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(3.000 ns) 4.500 ns quotient\[1\]~reg0 2 REG LC11 1 " "Info: 2: + IC(1.500 ns) + CELL(3.000 ns) = 4.500 ns; Loc. = LC11; Fanout = 1; REG Node = 'quotient\[1\]~reg0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { shift:u4|shiftin[1] quotient[1]~reg0 } "NODE_NAME" } } { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 70 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 66.67 % ) " "Info: Total cell delay = 3.000 ns ( 66.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 33.33 % ) " "Info: Total interconnect delay = 1.500 ns ( 33.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { shift:u4|shiftin[1] quotient[1]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.500 ns" { shift:u4|shiftin[1] {} quotient[1]~reg0 {} } { 0.000ns 1.500ns } { 0.000ns 3.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.000 ns - Smallest " "Info: - Smallest clock skew is -6.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.200 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns quotient\[1\]~reg0 2 REG LC11 1 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC11; Fanout = 1; REG Node = 'quotient\[1\]~reg0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk quotient[1]~reg0 } "NODE_NAME" } } { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 70 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 100.00 % ) " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk quotient[1]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} quotient[1]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.200 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns state_graph:u5\|srg4:u1\|srg_4\[0\] 2 REG LC9 9 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC9; Fanout = 9; REG Node = 'state_graph:u5\|srg4:u1\|srg_4\[0\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { clk state_graph:u5|srg4:u1|srg_4[0] } "NODE_NAME" } } { "srg4.vhd" "" { Text "D:/altera/myproject/dividend4/srg4.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(3.100 ns) 8.200 ns shift:u4\|shiftin\[1\] 3 REG LC20 2 " "Info: 3: + IC(1.500 ns) + CELL(3.100 ns) = 8.200 ns; Loc. = LC20; Fanout = 2; REG Node = 'shift:u4\|shiftin\[1\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { state_graph:u5|srg4:u1|srg_4[0] shift:u4|shiftin[1] } "NODE_NAME" } } { "shift.vhd" "" { Text "D:/altera/myproject/dividend4/shift.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns ( 81.71 % ) " "Info: Total cell delay = 6.700 ns ( 81.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 18.29 % ) " "Info: Total interconnect delay = 1.500 ns ( 18.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk state_graph:u5|srg4:u1|srg_4[0] shift:u4|shiftin[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.200 ns" { clk {} clk~out {} state_graph:u5|srg4:u1|srg_4[0] {} shift:u4|shiftin[1] {} } { 0.000ns 0.000ns 0.000ns 1.500ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk quotient[1]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} quotient[1]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk state_graph:u5|srg4:u1|srg_4[0] shift:u4|shiftin[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.200 ns" { clk {} clk~out {} state_graph:u5|srg4:u1|srg_4[0] {} shift:u4|shiftin[1] {} } { 0.000ns 0.000ns 0.000ns 1.500ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" { } { { "shift.vhd" "" { Text "D:/altera/myproject/dividend4/shift.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" { } { { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 70 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" { } { { "shift.vhd" "" { Text "D:/altera/myproject/dividend4/shift.vhd" 16 -1 0 } } { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 70 0 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { shift:u4|shiftin[1] quotient[1]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.500 ns" { shift:u4|shiftin[1] {} quotient[1]~reg0 {} } { 0.000ns 1.500ns } { 0.000ns 3.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk quotient[1]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} quotient[1]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk state_graph:u5|srg4:u1|srg_4[0] shift:u4|shiftin[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.200 ns" { clk {} clk~out {} state_graph:u5|srg4:u1|srg_4[0] {} shift:u4|shiftin[1] {} } { 0.000ns 0.000ns 0.000ns 1.500ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "state_graph:u5\|load shift:u4\|shiftin\[6\] clk 1.8 ns " "Info: Found hold time violation between source pin or register \"state_graph:u5\|load\" and destination pin or register \"shift:u4\|shiftin\[6\]\" for clock \"clk\" (Hold time is 1.8 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.000 ns + Largest " "Info: + Largest clock skew is 6.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.200 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns state_graph:u5\|srg4:u1\|srg_4\[0\] 2 REG LC9 9 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC9; Fanout = 9; REG Node = 'state_graph:u5\|srg4:u1\|srg_4\[0\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { clk state_graph:u5|srg4:u1|srg_4[0] } "NODE_NAME" } } { "srg4.vhd" "" { Text "D:/altera/myproject/dividend4/srg4.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(3.100 ns) 8.200 ns shift:u4\|shiftin\[6\] 3 REG LC36 9 " "Info: 3: + IC(1.500 ns) + CELL(3.100 ns) = 8.200 ns; Loc. = LC36; Fanout = 9; REG Node = 'shift:u4\|shiftin\[6\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { state_graph:u5|srg4:u1|srg_4[0] shift:u4|shiftin[6] } "NODE_NAME" } } { "shift.vhd" "" { Text "D:/altera/myproject/dividend4/shift.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns ( 81.71 % ) " "Info: Total cell delay = 6.700 ns ( 81.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 18.29 % ) " "Info: Total interconnect delay = 1.500 ns ( 18.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk state_graph:u5|srg4:u1|srg_4[0] shift:u4|shiftin[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.200 ns" { clk {} clk~out {} state_graph:u5|srg4:u1|srg_4[0] {} shift:u4|shiftin[6] {} } { 0.000ns 0.000ns 0.000ns 1.500ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.200 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns state_graph:u5\|load 2 REG LC18 34 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC18; Fanout = 34; REG Node = 'state_graph:u5\|load'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk state_graph:u5|load } "NODE_NAME" } } { "state_graph.vhd" "" { Text "D:/altera/myproject/dividend4/state_graph.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 100.00 % ) " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk state_graph:u5|load } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} state_graph:u5|load {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk state_graph:u5|srg4:u1|srg_4[0] shift:u4|shiftin[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.200 ns" { clk {} clk~out {} state_graph:u5|srg4:u1|srg_4[0] {} shift:u4|shiftin[6] {} } { 0.000ns 0.000ns 0.000ns 1.500ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk state_graph:u5|load } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} state_graph:u5|load {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns - " "Info: - Micro clock to output delay of source is 1.400 ns" { } { { "state_graph.vhd" "" { Text "D:/altera/myproject/dividend4/state_graph.vhd" 11 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.500 ns - Shortest register register " "Info: - Shortest register to register delay is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state_graph:u5\|load 1 REG LC18 34 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC18; Fanout = 34; REG Node = 'state_graph:u5\|load'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { state_graph:u5|load } "NODE_NAME" } } { "state_graph.vhd" "" { Text "D:/altera/myproject/dividend4/state_graph.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(3.000 ns) 4.500 ns shift:u4\|shiftin\[6\] 2 REG LC36 9 " "Info: 2: + IC(1.500 ns) + CELL(3.000 ns) = 4.500 ns; Loc. = LC36; Fanout = 9; REG Node = 'shift:u4\|shiftin\[6\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { state_graph:u5|load shift:u4|shiftin[6] } "NODE_NAME" } } { "shift.vhd" "" { Text "D:/altera/myproject/dividend4/shift.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 66.67 % ) " "Info: Total cell delay = 3.000 ns ( 66.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 33.33 % ) " "Info: Total interconnect delay = 1.500 ns ( 33.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { state_graph:u5|load shift:u4|shiftin[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.500 ns" { state_graph:u5|load {} shift:u4|shiftin[6] {} } { 0.000ns 1.500ns } { 0.000ns 3.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" { } { { "shift.vhd" "" { Text "D:/altera/myproject/dividend4/shift.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk state_graph:u5|srg4:u1|srg_4[0] shift:u4|shiftin[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.200 ns" { clk {} clk~out {} state_graph:u5|srg4:u1|srg_4[0] {} shift:u4|shiftin[6] {} } { 0.000ns 0.000ns 0.000ns 1.500ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk state_graph:u5|load } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} state_graph:u5|load {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { state_graph:u5|load shift:u4|shiftin[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.500 ns" { state_graph:u5|load {} shift:u4|shiftin[6] {} } { 0.000ns 1.500ns } { 0.000ns 3.000ns } "" } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "state_graph:u5\|input st clk 3.400 ns register " "Info: tsu for register \"state_graph:u5\|input\" (data pin = \"st\", clock pin = \"clk\") is 3.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.600 ns + Longest pin register " "Info: + Longest pin to register delay is 4.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns st 1 PIN PIN_25 3 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_25; Fanout = 3; PIN Node = 'st'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { st } "NODE_NAME" } } { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.000 ns) 4.600 ns state_graph:u5\|input 2 REG LC25 2 " "Info: 2: + IC(1.400 ns) + CELL(3.000 ns) = 4.600 ns; Loc. = LC25; Fanout = 2; REG Node = 'state_graph:u5\|input'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { st state_graph:u5|input } "NODE_NAME" } } { "state_graph.vhd" "" { Text "D:/altera/myproject/dividend4/state_graph.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 69.57 % ) " "Info: Total cell delay = 3.200 ns ( 69.57 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 30.43 % ) " "Info: Total interconnect delay = 1.400 ns ( 30.43 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { st state_graph:u5|input } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.600 ns" { st {} st~out {} state_graph:u5|input {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" { } { { "state_graph.vhd" "" { Text "D:/altera/myproject/dividend4/state_graph.vhd" 23 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.200 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns state_graph:u5\|input 2 REG LC25 2 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC25; Fanout = 2; REG Node = 'state_graph:u5\|input'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk state_graph:u5|input } "NODE_NAME" } } { "state_graph.vhd" "" { Text "D:/altera/myproject/dividend4/state_graph.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 100.00 % ) " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk state_graph:u5|input } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} state_graph:u5|input {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { st state_graph:u5|input } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.600 ns" { st {} st~out {} state_graph:u5|input {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk state_graph:u5|input } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} state_graph:u5|input {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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