library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count8 is
port(clk:in std_logic;
q1:out std_logic_vector(2 downto 0)
);
end count8;
architecture rt1 of count8 is
signal qc1:std_logic_vector(2 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1')then
if(qc1="111")then
qc1<="000";
else
qc1<=qc1+'1';
end if;
end if;
end process;
q1<=qc1;
end rt1;