+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;     100.00 % ;
; Total nodes checked                                 ; 23           ;
; Total output ports checked                          ; 34           ;
; Total output ports with complete 1/0-value coverage ; 34           ;
; Total output ports with no 1/0-value coverage       ; 0            ;
; Total output ports with no 1-value coverage         ; 0            ;
; Total output ports with no 0-value coverage         ; 0            ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                    ;
+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------+
; Node Name                                                                               ; Output Port Name                                                                  ; Output Port Type ;
+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------+
; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0 ; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[0] ; portadataout0    ;
; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0 ; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[1] ; portadataout1    ;
; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0 ; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[2] ; portadataout2    ;
; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0 ; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[3] ; portadataout3    ;
; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0 ; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[4] ; portadataout4    ;
; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0 ; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[5] ; portadataout5    ;
; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0 ; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[6] ; portadataout6    ;
; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0 ; |rom|sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[7] ; portadataout7    ;
; |rom|count:u0|Add0~85                                                                   ; |rom|count:u0|Add0~85                                                             ; sumout           ;
; |rom|count:u0|Add0~85                                                                   ; |rom|count:u0|Add0~86                                                             ; cout             ;
; |rom|count:u0|Add0~89                                                                   ; |rom|count:u0|Add0~89                                                             ; sumout           ;
; |rom|count:u0|Add0~89                                                                   ; |rom|count:u0|Add0~90                                                             ; cout             ;
; |rom|count:u0|Add0~93                                                                   ; |rom|count:u0|Add0~93                                                             ; sumout           ;
; |rom|count:u0|Add0~93                                                                   ; |rom|count:u0|Add0~94                                                             ; cout             ;
; |rom|count:u0|Add0~97                                                                   ; |rom|count:u0|Add0~97                                                             ; sumout           ;
; |rom|count:u0|Add0~97                                                                   ; |rom|count:u0|Add0~98                                                             ; cout             ;
; |rom|count:u0|Add0~101                                                                  ; |rom|count:u0|Add0~101                                                            ; sumout           ;
; |rom|count:u0|countt[0]                                                                 ; |rom|count:u0|countt[0]                                                           ; regout           ;
; |rom|count:u0|countt[1]                                                                 ; |rom|count:u0|countt[1]                                                           ; regout           ;
; |rom|count:u0|countt[2]                                                                 ; |rom|count:u0|countt[2]                                                           ; regout           ;
; |rom|count:u0|countt[3]                                                                 ; |rom|count:u0|countt[3]                                                           ; regout           ;
; |rom|count:u0|countt[4]                                                                 ; |rom|count:u0|countt[4]                                                           ; regout           ;
; |rom|count:u0|countt[5]                                                                 ; |rom|count:u0|countt[5]                                                           ; regout           ;
; |rom|count:u0|countt[0]~14                                                              ; |rom|count:u0|countt[0]~14                                                        ; combout          ;
; |rom|q[0]                                                                               ; |rom|q[0]                                                                         ; padio            ;
; |rom|q[1]                                                                               ; |rom|q[1]                                                                         ; padio            ;
; |rom|q[2]                                                                               ; |rom|q[2]                                                                         ; padio            ;
; |rom|q[3]                                                                               ; |rom|q[3]                                                                         ; padio            ;
; |rom|q[4]                                                                               ; |rom|q[4]                                                                         ; padio            ;
; |rom|q[5]                                                                               ; |rom|q[5]                                                                         ; padio            ;
; |rom|q[6]                                                                               ; |rom|q[6]                                                                         ; padio            ;
; |rom|q[7]                                                                               ; |rom|q[7]                                                                         ; padio            ;
; |rom|clock                                                                              ; |rom|clock~corein                                                                 ; combout          ;
; |rom|clock~clkctrl                                                                      ; |rom|clock~clkctrl                                                                ; outclk           ;
+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------+
; Missing 1-Value Coverage                        ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------+
; Missing 0-Value Coverage                        ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Jan 01 15:51:06 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off rom -c rom
Info: Using vector source file "E:/課件/VHDL/code/sinx/ROM4/rom.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is     100.00 %
Info: Number of transitions in simulation is 1926
Info: Thank you for using the Quartus II software 30-day evaluation. You have 3 days left (until Jan 04, 2009) before compilation and simulation support is disabled.
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 99 megabytes of memory during processing
    Info: Processing ended: Thu Jan 01 15:51:07 2009
    Info: Elapsed time: 00:00:01