-- **************************************************************
-- File:  		command_state_machine.vhd
--
-- Purpose: 	Recognizes user play functions, i.e. rewind, fast
--			forward, stop and play operations. Interfaces to
--			flash control to read from starting address and 
--			song flash modules.  Loads song address counter
--			on rewind, fwd and play operatins.
--	
-- Created:		10-28-99 JLJ
-- Revised:		11-4-99 ALS
-- Revised:		11-5-99 ALS
-- Revised:		11-12-99 JLJ & ALS
-- Revised:		11-14-99 ALS
-- **************************************************************


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity command_state_machine is
    port(
        
        clock		: in STD_LOGIC;
        reset		: in STD_LOGIC;
                        
	  -- User commands from Main Control logic
	  rew			: in STD_LOGIC;		-- Asserted high for rewind operation
	  fwd			: in STD_LOGIC;		-- Asserted high for fast forward opertion
	  stop		: in STD_LOGIC;		-- Asserted high for stop opertion

        read_stadr	: out STD_LOGIC;		-- Asserted to read from Starting Address Flash: 
								-- 16 bit wide read when read_stadr = 1
	
	  -- Change starting address counter
	  stadr_inc 	: out STD_LOGIC;		-- Asserted on fast forward operation	
	  stadr_dec		: out STD_LOGIC;		-- Asserted on rewind operation
	  cmd_song_end	: out STD_LOGIC;		-- Asserted when a fast forward gets to the end of song data
	  end_flag_com	: in	STD_LOGIC;		-- Asserted when upper starting address bits match END_DATA
								-- signifies that end of song data is coming

	  -- Data from starting address counter
	  track		: in STD_LOGIC_VECTOR(4 downto 0);  -- Track Number

	  -- Load song address counter during rew, fwd, and stop operations
	  adr_ld_l		: out STD_LOGIC;		-- Asserted to write lower byte (15:0) of counter
	  adr_ld_u		: out STD_LOGIC;		-- Asserted to write upper byte (32:16) of counter

	  flash_done	: out STD_LOGIC		-- Asserted when rew/fwd/stop operation complete
								-- and song address counter is loaded and ready for
								-- play/read commands
        );

end command_state_machine;


architecture BEHAVIOURAL of command_state_machine is

-- ******************** CONSTANT DECLARATIONS ***********************
constant RESET_ACTIVE 	: STD_LOGIC := '1';
constant ALL_ZEROS	: STD_LOGIC_VECTOR(4 downto 0) := "00000";

-- ********************* SIGNAL DECLARATIONS ************************

-- Define state type for write/erase and read state machine
type STATE is (IDLE, CHK_TRACK, DEC1, DEC2, WAIT_DEC, TRACK_NUM, 
		   WT_TRACK, READ_ADR, LOAD_ADR, WAIT_ADR, WAIT_RD_INC, DONE);

-- States for write/erase and read state machine
signal prs_state, nxt_state : STATE;

-- When track number is odd, need to decrement the track number
signal odd_tracknum : std_logic;


begin
	-- ***************** SIGNAL DEFINITION *************************
	
	stadr_inc <= '1' when (fwd = '1') and (prs_state = TRACK_NUM) else '0';
	stadr_dec <= '1' when (((rew = '1') and (prs_state = TRACK_NUM))
				or (odd_tracknum = '1')
				or (prs_state = DEC1)
				or (prs_state = DEC2) )
				else '0';

	flash_done <= '1' when (prs_state = DONE) else '0';
	

	-- ***************** Process: SEQUENTIAL ************************
	-- Purpose:  	Synchronize write_erase and read target state machines
	-- Components: 	none
    
    	SEQUENTIAL: process (reset, clock)
    	begin
     		if reset = RESET_ACTIVE then	
            	prs_state <= IDLE;

        	elsif clock'event and (clock = '1') then
            	prs_state <= nxt_state;
            
        	end if;

    	end process SEQUENTIAL;
    
    

    -- ***************** Process: COMMAND_SM ************************
    -- Purpose:	Manages the changing and loading track number of 
    --		starting address flash into song flash counter.
    --		Interprets rewind, fast forward, and stop operations. 
    -- Components:  none
        
    COMMAND_SM: process (prs_state, rew, fwd, stop, track, end_flag_com)
    begin
    
	 read_stadr <= '0';
	 flash_done <= '0';
	 adr_ld_l <= '0';
	 adr_ld_u <= '0';
    	 nxt_state <= prs_state;
	 cmd_song_end <= '0';
	 odd_tracknum <= '0';

    	
        case prs_state is
        
        	----------------------- IDLE State --------------------------
        	when IDLE =>

			-- Wait for rewind, fast forward or stop command
			if (rew = '1') or (fwd = '1') or (stop = '1') then
				nxt_state <= CHK_TRACK;
			end if;
	
		--------------------- CHK_TRACK State ------------------------
		when CHK_TRACK =>
			-- this state checks the track number to see if its pointing
			-- to the upper or lower song address. Upper song addresses
			-- are stored at even locations, lower song addresses are stored
			-- at odd locations, one greater than the upper location
			-- if the track number is odd, set the odd_tracknum signal
			-- so that the number is decremented
			if track(0) = '1' then 
				odd_tracknum <= '1';
			end if;

			-- start decrmenting the track number to get it to the present track
			nxt_state <= DEC1;

		------------------------- DEC1 State --------------------------------
		when DEC1 =>
			-- in this state, the track number is decremented
			-- go to the DEC2 state to decrement the next byte
			nxt_state <= DEC2;

		-------------------------- DEC2 State -------------------------------
		when DEC2 =>
			-- in this state, the track number is decremented 
			-- go to the WAIT_DEC state for the decrement to take effect
			nxt_state <= WAIT_DEC;

		--------------------------- WAIT_DEC --------------------------------
		when WAIT_DEC =>
			-- this state provides a 1-clock delay to allow the counter to decrement
			-- go to the tracknum state to either increment or decrement the 
			-- track number based on the command
			-- if command is stop, just go to WAIT_ADR state, no adjustment
			-- to the track number is needed
			if stop = '1' then
				nxt_state <= WAIT_ADR;
			else
				nxt_state <= TRACK_NUM;
			end if;        	
        	--------------------- TRACK_NUM State -----------------------
        	when TRACK_NUM =>

			-- Increments or decrements track number
			-- Must increment starting address counter by 2
			-- since each track number is 32 bits wide
			-- if track number is all zeros and rewind, then skip to WAIT_ADR state
			-- counter will not decrement below zero
			if track = ALL_ZEROS and rew = '1' then
				nxt_state <= WAIT_ADR;
			elsif (track(0) = '0') then
				-- upper byte	
				nxt_state <= WT_TRACK;
			else 
				nxt_state <= WAIT_ADR;
			end if;

    		--------------------- WT_TRACK State -----------------------
        	when WT_TRACK =>
			-- this state allows adjustments to the track number to
			-- take effect

			nxt_state <= TRACK_NUM;


		---------------------- WAIT_ADR State ------------------------
        	when WAIT_ADR =>
			
			read_stadr <= '0';
			nxt_state <= READ_ADR;


        	---------------------- READ_ADR State ------------------------
        	when READ_ADR =>
			
			-- Read from Starting Address Flash
			read_stadr <= '0';
			nxt_state <= LOAD_ADR;  			       	
        	
        	
        	-------------------- LOAD_ADR State ------------------------
        	when LOAD_ADR =>
			
			-- Load song address counter to start next play/read
			read_stadr <= '1';

			-- if loading upper byte, check for end of data flag
			if track(0) = '0' then
				-- loading upper byte
				if end_flag_com = '1' then

					-- data read from starting address flash indicates the 
					-- end of song data has been reached
					-- assert cmd_song_end and this goes to the FLASH_CNTR logic
					-- and resets both the track number and the song flash address
					-- counter, therefore there is no need to load the counters
					cmd_song_end <= '1';
					nxt_state <= DONE;
				else
					-- not end of data
					adr_ld_u <= '1';
					nxt_state <= WAIT_RD_INC;
				end if;
		
			
			else
				-- Load lower bytes of address counter
				adr_ld_l <= '1';
				nxt_state <= DONE;
	
			end if;
		
		-------------------- WAIT_RD_INC ---------------------------
		when WAIT_RD_INC =>
			-- this state waits for the increment to the track number
			-- from the read state machine to take affect 	
			nxt_state <= WAIT_ADR;
			
	
        	-------------------- DONE State ------------------------
        	when DONE =>
			
			flash_done <= '1';		
    			nxt_state <= IDLE;		
 
        	    	
        end case;  
        
    end process COMMAND_SM;
   


end BEHAVIOURAL;