/*
Copyright -c- 1996, Kluwer Academic Publishers. All Rights Reserved.

This electronic text file is distributed by Kluwer Academic Publishers with
*ABSOLUTELY NO SUPPORT* and *NO WARRANTY* from Kluwer
Academic Publishers.

Use or reproduction of the information provided in this electronic text file for

commercial gain is strictly prohibited. Explicit permission is given for the
reproduction and use of this information in an instructional setting provided
proper reference is given to the original source. Kluwer Academic Publishers
shall not be liable for damage in connection with, or arising out of, the furnis
hing,
performance or use of this information.


From the Authors:
This file contains copies of most of the examples in chapters 1 through 8 of "Th
e
Verilog Hardware Description Language, Third Edition" by D. E. Thomas and P.
R. Moorby. Note that several corrections have been made to the examples in this
file and thus they may differ from the examples in the book. Later printings of 
the
book will include these corrections.

This file, itself, cannot be simulated because several module names are
duplicated in different examples. However, the examples may be extracted and
simulated. The book example numbers are indicated below the example text. A
few of the examples are not included because they were not meant to be fully
simulatable. 

-always
        DT, PM
*/




module ffNand;
        wire            q, qBar;
        reg             preset, clear;

        nand #1
                g1 (q, qBar, preset),
                g2 (qBar, q, clear);
endmodule

//example 1.1




module ffNandSim;
        wire            q, qBar; 
        reg             preset, clear; 

        nand #1
                g1 (q, qBar, preset),
                g2 (qBar, q, clear);

        initial 
                begin
                        // two slashes introduce a single line comment
                        $monitor ($time,, 
                                "Preset = %b clear = %b q = %b qBar = %b",
                                preset, clear, q, qBar);
                        //waveform for simulating the nand flip flop
                        #10 preset = 0; clear = 1;
                        #10 preset = 1;
                        #10 clear = 0;
                        #10 clear = 1;
                        #10 $finish;
                end
endmodule

//example 1.2




module m16 (value, clock, fifteen, altFifteen);
        output          [3:0]           value;
        output                  fifteen,
                                altFifteen;
        input                   clock;

        dEdgeFF                 a (value[0], clock, ~value[0]),
                                b (value[1], clock, value[1] ^ value[0]),
                                c (value[2], clock, value[2] ^ &value[1:0]),
                                d (value[3], clock, value[3] ^ &value[2:0]);

        assign fifteen = value[0] & value[1] & value[2] & value[3];
        assign altFifteen = &value;
endmodule
//example 1.3




module dEdgeFF (q, clock, data);
        output          q;
        reg             q;
        input           clock, data;

        initial
                #10 q = 0;

        always
                @(negedge clock) #10 q = data;

endmodule
//example 1.4




module m555 (clock);
        output          clock;
        reg             clock;

        initial
                #5 clock = 1;

        always
                #50 clock = ~ clock;
endmodule
//example 1.5




module board;
        wire            [3:0]           count;
        wire                            clock,
                                        f,
                                        af;

        m16             counter (count, clock, f, af);
        m555            clockGen (clock);

        always @ (posedge clock)
                $display ($time,,,"count=%d, f=%d, af=%d", count, f, af);
endmodule
//example 1.6




module dEdgeFF (q, clock, data);
        input           clock, data;
        output          q;
        reg             reset;
        wire            q, qBar, r, s, r1, s1;

        initial begin
                reset = 1;
                #20 reset = 0;
        end

        nor #10
                a (q, qBar, r, reset);
        nor
                b (qBar, q, s),
                c (s, r, clock, s1),
                d (s1, s, data),
                e (r, r1, clock),
                f (r1, s1, r);

endmodule
//example 1.7




module m16Behav (value, clock, fifteen, altFifteen);
        output          [3:0]           value;
        reg             [3:0]           value;
        output                          fifteen,
                                        altFifteen;
        reg                             fifteen,
                                        altFifteen;
        input                           clock;

        initial
                value = 0;

        always
                begin
                        @(negedge clock) #10 value = value + 1;
                        if (value == 15)
                                begin
                                        altFifteen = 1;
                                        fifteen = 1;
                                end
                        else
                                begin
                                        altFifteen = 0;
                                        fifteen = 0;
                                end
                end
endmodule
// example 1.8
module top();
        wire                    flag, numProduced, numConsumed;
        wire            [15:0]  number, numberOut;

        nandLatch                               ready (flag, , numConsumed, 
numProduced);
        numberGen                               ng (number, numProduced, flag);
        fibNumberGen                            fng (number, flag, numConsumed, 
numberOut);
endmodule
//example 1.9




module nandLatch (q, qBar, set, reset);
        output          q, qBar;
        input           set, reset;

        nand #2
                (q, qBar, set),
                (qBar, q, reset);
endmodule
//example 1.10




module numberGen (number, numProduced, flag);
        output          [15:0]          number;
        output                          numProduced;
        input                           flag;

        reg                             numProduced;
        reg             [15:0]          number;

        initial
                begin
                        number = 0;
                        numProduced = 1;
                end

        always
                begin
                        wait (flag == 1)
                                number = number + 1;
                        #100 numProduced = 0;
                        #10 numProduced = 1;
                end
endmodule
//example 1.11




module fibNumberGen (startingValue, flag, numConsumed,fibNum); 
        input           [15:0]          startingValue;
        input                           flag;
        output                          numConsumed;
        output          [15:0]          fibNum;

        reg                             numConsumed;
        reg             [15:0]          count, fibNum, oldNum, temp;

        initial
                begin
                        numConsumed = 0;
                        #10 numConsumed = 1;
                        $monitor ($time,,"fibNum=%d, startingValue=%d", 
fibNum, startingValue);
                end

        always
                begin
                        wait (flag == 0)
                                count = startingValue;
                        oldNum = 1;
                        numConsumed = 0;
                        #10 numConsumed = 1;    //signal ready for input

                        for (fibNum = 0; count != 0; count = count - 1)
                                begin
                                        temp = fibNum;
                                        fibNum = fibNum + oldNum;
                                        oldNum = temp;
                                end
                        $display ("%d fibNum=%d", $time, fibNum);
                end
endmodule
//example 1.12




`define DvLen 15
`define DdLen 31
`define QLen 15
`define HiDdMin 16

module divide (ddInput, dvInput, quotient, go, done);
input           [`DdLen:0]                      ddInput;
input           [`DvLen:0]                      dvInput;
output          [`QLen:0]                       quotient;
input                                   go;
output                                  done;

reg     [`DdLen:0]                      dividend;
reg     [`QLen:0]                       quotient;
reg     [`DvLen:0]                      divisor;
reg                             done,
                                negDivisor, 
                                negDividend;

initial
        done = 0;

always
        begin
                wait (go);
                divisor = dvInput;
                dividend = ddInput;
                quotient = 0;
                if (divisor)
                        begin
                                negDivisor = divisor[`DvLen];
                                if (negDivisor)
                                        divisor = - divisor;
                                negDividend = dividend[`DdLen];
                                if (negDividend)
                                        dividend = - dividend;
                                repeat (`DvLen + 1)
                                        begin
                                                quotient = quotient << 1;
                                                dividend = dividend << 1;
                                                dividend[`DdLen:`HiDdMin] = 
                                                        dividend[`DdLen:`HiDdMin] 
- divisor;
                                                if (! dividend [`DdLen])
                                                        quotient = quotient + 1;
                                                else    
                                                        dividend[`DdLen:`HiDdMin] 
= 
                                                                dividend[`DdLen:
`HiDdMin] + divisor;
                                        end
                                if (negDivisor != negDividend)
                                        quotient = - quotient;
                        end
                done = 1;
                wait (~go);
        end
endmodule
//example 2.1




module mark1;
reg [31:0]                      m [0:8191];                             // 8192 x 32 
bit memory
reg [12:0]                      pc;                             // 13 bit program 
counter
reg [31:0]                      acc;                            // 32 bit accumulator
reg [15:0]                      ir;                             // 16 bit instruction 
register

        always 
                begin
                        ir = m [pc];                                            // 
fetch an instruction
                        if (ir[15:13] == 3'b000)                                                
// begin decoding
                                pc = m [ir [12:0]];                                     
// and executing
                        else if (ir[15:13] == 3'b001)
                                pc = pc + m [ir [12:0]];
                        else if (ir[15:13] == 3'b010)
                                acc = -m [ir [12:0]];
                        else if (ir[15:13] == 3'b011)
                                m [ir [12:0]] = acc;
                        else if ((ir[15:13] == 3'b101) || (ir[15:13] == 3'b100))
                                acc = acc - m [ir [12:0]];
                        else if (ir[15:13] == 3'b110)
                                if (acc < 0) pc = pc + 1;
                        #1 pc = pc + 1;                                         
//increment program
                                                                        // 
counter and time
                end
endmodule
//example 2.5




module mark1Case;
reg [31:0]                      m [0:8191];                             // 8192 x 32 
bit memory 
reg [12:0               ]       pc;                             // 13 bit program 
counter 
reg [31:0]                      acc;                            // 32 bit accumulator
reg [15:0]                      ir;                             // 16 bit instruction 
register

        always 
                begin
                        ir = m [pc];
                        case (ir [15:13])
                                3'b000 :                        pc = m [ir [12:0]];
                                3'b001 :                        pc = pc + m [ir 
[12:0]];
                                3'b010 :                        acc = -m [ir [12:0]];
                                3'b011 :                        m [ir [12:0]] = acc;
                                3'b100,
                                3'b101 :                        acc = acc - m [ir 
[12:0]];
                                3'b110 :                        if (acc < 0) pc = pc 
+ 1;
                        endcase
                        #1 pc = pc + 1;
                end
endmodule
//example 2.6





module mark1Mult;
reg [31:0]                      m [0:8191];                             // 8192 x 32 
bit memory
reg [12:0]                      pc;                             // 13 bit program