<!--
This XML file (created on Mon Apr 07 12:44:05 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.0</ver>
<schema>quartus_version_5.0_build_148.xsd</schema><license>
	<nic_id>00e04c71b683</nic_id>
	<cdrive_id>205b19dd</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.0</version>
	<build>Build 148</build>
	<module>quartus_sim.exe</module>
	<edition>Web Edition (Eval)</edition>
	<compilation_end_time>Mon Apr 07 12:44:06 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">849</cpu_freq>
	</cpu>
	<ram units="MB">512</ram>
</machine>
<top_file>F:/FPGA/test/test1</top_file>
<mep_data>
	<command_line>quartus_sim --read_settings_files=on --write_settings_files=off test -c test1</command_line>
</mep_data>
<messages>
	<warning>Warning: Can&apos;t find signal in vector source file for input pin &quot;|test1|a[7]&quot;</warning>
	<warning>Warning: Can&apos;t find signal in vector source file for input pin &quot;|test1|a[6]&quot;</warning>
	<warning>Warning: Can&apos;t find signal in vector source file for input pin &quot;|test1|a[5]&quot;</warning>
	<warning>Warning: Can&apos;t find signal in vector source file for input pin &quot;|test1|a[4]&quot;</warning>
	<warning>Warning: Can&apos;t find signal in vector source file for input pin &quot;|test1|a[3]&quot;</warning>
	<info>Info: Quartus II Simulator was successful. 0 errors, 9 warnings</info>
	<info>Info: Elapsed time: 00:00:02</info>
	<info>Info: Processing ended: Mon Apr 07 12:44:05 2008</info>
	<info>Info: Number of transitions in simulation is 0</info>
	<info>Info: Simulation coverage is       0.00 %</info>
</messages>
<simulator_summary>
	<simulation_start_time>0 ps</simulation_start_time>
	<simulation_end_time>1.0 us</simulation_end_time>
	<simulation_netlist_size>16 nodes</simulation_netlist_size>
	<simulation_coverage>      0.00 %</simulation_coverage>
	<total_number_of_transitions>0</total_number_of_transitions>
</simulator_summary>
<compile_id>EEB12F01</compile_id>
</talkback>