Simulator report for test1
Mon Apr 07 12:44:06 2008
Version 5.0 Build 148 04/26/2005 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. Simulator INI Usage
  6. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------+
; Simulator Summary                          ;
+-----------------------------+--------------+
; Type                        ; Value        ;
+-----------------------------+--------------+
; Simulation Start Time       ; 0 ps         ;
; Simulation End Time         ; 1.0 us       ;
; Simulation Netlist Size     ; 16 nodes     ;
; Simulation Coverage         ;       0.00 % ;
; Total Number of Transitions ; 0            ;
+-----------------------------+--------------+


+--------------------------------------------------------------------+
; Simulator Settings                                                 ;
+-------------------------------------------------------+------------+
; Option                                                ; Setting    ;
+-------------------------------------------------------+------------+
; Simulation mode                                       ; Functional ;
; Start time                                            ; 0ns        ;
; Add pins automatically to simulation output waveforms ; On         ;
; Check outputs                                         ; Off        ;
; Report simulation coverage                            ; On         ;
; Detect setup and hold time violations                 ; Off        ;
; Detect glitches                                       ; Off        ;
; Automatically save/load simulation netlist            ; Off        ;
; Disable timing delays in Timing Simulation            ; Off        ;
; Generate Signal Activity File                         ; Off        ;
+-------------------------------------------------------+------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 5.0 Build 148 04/26/2005 SJ Web Edition
    Info: Processing started: Mon Apr 07 12:44:04 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off test -c test1
Warning: Ignored node in vector source file. Can't find corresponding node name "clkin" in design.
Warning: Can't find signal in vector source file for input pin "|test1|a[0]"
Warning: Can't find signal in vector source file for input pin "|test1|a[1]"
Warning: Can't find signal in vector source file for input pin "|test1|a[2]"
Warning: Can't find signal in vector source file for input pin "|test1|a[3]"
Warning: Can't find signal in vector source file for input pin "|test1|a[4]"
Warning: Can't find signal in vector source file for input pin "|test1|a[5]"
Warning: Can't find signal in vector source file for input pin "|test1|a[6]"
Warning: Can't find signal in vector source file for input pin "|test1|a[7]"
Info: Simulation coverage is       0.00 %
Info: Number of transitions in simulation is 0
Info: Quartus II Simulator was successful. 0 errors, 9 warnings
    Info: Processing ended: Mon Apr 07 12:44:05 2008
    Info: Elapsed time: 00:00:02