library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity second is
port(clk,clr:in std_logic;
sec1,sec0:out std_logic_vector(3 downto 0);
co:out std_logic);
end second;
architecture art of second is
begin
process(clk,clr)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clr='1' then
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
	if cnt1="0101" and cnt0="1001"then
		co<='1';
		cnt1:="0000";
		cnt0:="0000";
		
	elsif cnt0<"1001"then
		cnt0:=cnt0+1;
        co<='0';
	else
		cnt0:="0000";
		if cnt1<"0101" then
   			cnt1:=cnt1+1;
            co<='0';
		else
			cnt1:="0000";
			co<='0';
		end if;
	end if;
end if;

sec1<=cnt1;
sec0<=cnt0;
end process;
end art;