?? lcd.rpt
字號:
B11 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
B12 8/ 8(100%) 4/ 8( 50%) 0/ 8( 0%) 0/2 0/2 16/22( 72%)
B13 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B14 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
B15 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C2 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 2/22( 9%)
C6 4/ 8( 50%) 4/ 8( 50%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
C15 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
C19 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 12/22( 54%)
C26 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 13/22( 59%)
C28 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 4/22( 18%)
D1 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
D2 8/ 8(100%) 6/ 8( 75%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
D3 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
D4 8/ 8(100%) 6/ 8( 75%) 5/ 8( 62%) 0/2 0/2 10/22( 45%)
D5 4/ 8( 50%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
D6 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 14/22( 63%)
D7 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
D8 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 16/22( 72%)
D9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
D10 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 0/2 0/2 14/22( 63%)
D11 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
D12 8/ 8(100%) 4/ 8( 50%) 3/ 8( 37%) 0/2 0/2 14/22( 63%)
D13 7/ 8( 87%) 4/ 8( 50%) 1/ 8( 12%) 0/2 0/2 16/22( 72%)
D14 4/ 8( 50%) 4/ 8( 50%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
D15 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 13/22( 59%)
D16 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 20/22( 90%)
D17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
D18 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
D21 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 13/22( 59%)
D25 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
D26 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 4/22( 18%)
D30 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 18/22( 81%)
E3 8/ 8(100%) 6/ 8( 75%) 2/ 8( 25%) 1/2 1/2 4/22( 18%)
E9 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 6/22( 27%)
E15 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 3/22( 13%)
E17 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 1/2 1/2 7/22( 31%)
E18 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 1/2 1/2 6/22( 27%)
E22 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 2/22( 9%)
E24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
E26 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 6/22( 27%)
E28 4/ 8( 50%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 5/22( 22%)
E29 7/ 8( 87%) 2/ 8( 25%) 0/ 8( 0%) 1/2 1/2 8/22( 36%)
E30 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 6/22( 27%)
E31 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 3/22( 13%)
E32 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 6/22( 27%)
E33 5/ 8( 62%) 2/ 8( 25%) 4/ 8( 50%) 1/2 1/2 5/22( 22%)
E35 8/ 8(100%) 6/ 8( 75%) 3/ 8( 37%) 1/2 1/2 10/22( 45%)
E36 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 6/22( 27%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 15/141 ( 10%)
Total logic cells used: 578/1728 ( 33%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.21/4 ( 80%)
Total fan-in: 1856/6912 ( 26%)
Total input pins required: 2
Total input I/O cell registers required: 0
Total output pins required: 14
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 578
Total flipflops required: 97
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 393/1728 ( 22%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 8 8 8 8 8 8 8 8 8 8 8 8 7 3 7 8 8 8 0 7 5 7 8 6 8 8 4 7 7 8 8 8 8 2 8 8 8 262/0
B: 8 8 0 0 1 5 1 8 8 1 1 8 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54/0
C: 0 8 0 0 0 4 0 0 0 0 0 0 0 0 7 0 0 0 0 6 0 0 0 0 0 0 8 0 2 0 0 0 0 0 0 0 0 35/0
D: 1 8 8 8 4 8 8 7 1 8 8 8 7 4 8 8 1 1 0 0 0 8 0 0 0 1 2 0 0 0 7 0 0 0 0 0 0 124/0
E: 0 0 8 0 0 0 0 0 8 0 0 0 0 0 1 0 8 8 0 0 0 0 7 0 1 0 8 0 4 7 8 8 7 5 0 8 7 103/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 17 32 24 16 13 25 17 23 25 17 17 24 15 8 24 17 18 17 0 13 5 15 15 6 9 9 22 7 13 15 23 16 15 7 8 16 15 578/0
Device-Specific Information:f:\work\fpga_platform\fpga_evm\20041113\lcd_max\lcd_max_wrapper\lcd.rpt
lcd
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G ^ 0 0 0 0 clk
180 - - - 18 INPUT ^ 0 0 0 89 rst
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:f:\work\fpga_platform\fpga_evm\20041113\lcd_max\lcd_max_wrapper\lcd.rpt
lcd
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
121 - - E -- OUTPUT 0 1 0 0 cs1
122 - - E -- OUTPUT 0 1 0 0 cs2
133 - - C -- OUTPUT 0 1 0 0 db0
134 - - C -- OUTPUT 0 1 0 0 db1
131 - - C -- OUTPUT 0 1 0 0 db2
132 - - C -- OUTPUT 0 1 0 0 db3
127 - - D -- OUTPUT 0 1 0 0 db4
128 - - D -- OUTPUT 0 1 0 0 db5
125 - - D -- OUTPUT 0 1 0 0 db6
126 - - D -- OUTPUT 0 1 0 0 db7
136 - - C -- OUTPUT 0 1 0 0 e
139 - - B -- OUTPUT 0 1 0 0 rs
119 - - E -- OPNDRN 0 1 0 0 rstb
135 - - C -- OUTPUT 0 0 0 0 rw
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
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