?? jiu.vhd
字號:
--揪 (脈沖寬度由窄變寬,脈沖組的間隔由長變短)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jiu is
port(clk:in std_logic;
outp:out integer range 0 to 1023);
end jiu;
ARCHITECTURE rtl OF jiu IS
signal data:integer;
signal tmp:integer range 63 downto 0;
begin
outp<=data;
process(clk)
begin
if(clk'event and clk='1') then
tmp<=tmp+1;
case tmp is
when 00=>data<=0;
when 01=>data<=0;
when 02=>data<=0;
when 03=>data<=0;
when 04=>data<=0;
when 05=>data<=0;
when 06=>data<=0;
when 07=>data<=1023;
when 08=>data<=1023;
when 09=>data<=1023;
when 10=>data<=0;
when 11=>data<=0;
when 12=>data<=0;
when 13=>data<=0;
when 14=>data<=0;
when 15=>data<=0;
when 16=>data<=0;
when 17=>data<=1023;
when 18=>data<=1023;
when 19=>data<=1023;
when 20=>data<=0;
when 21=>data<=0;
when 22=>data<=0;
when 23=>data<=0;
when 24=>data<=0;
when 25=>data<=1023;
when 26=>data<=1023;
when 27=>data<=1023;
when 28=>data<=1023;
when 29=>data<=1023;
when 30=>data<=0;
when 31=>data<=0;
when 32=>data<=0;
when 33=>data<=0;
when 34=>data<=0;
when 35=>data<=1023;
when 36=>data<=1023;
when 37=>data<=1023;
when 38=>data<=1023;
when 39=>data<=1023;
when 40=>data<=0;
when 41=>data<=0;
when 42=>data<=0;
when 43=>data<=1023;
when 44=>data<=1023;
when 45=>data<=1023;
when 46=>data<=1023;
when 47=>data<=1023;
when 48=>data<=1023;
when 49=>data<=1023;
when 50=>data<=1023;
when 51=>data<=1023;
when 52=>data<=0;
when 53=>data<=0;
when 54=>data<=0;
when 55=>data<=1023;
when 56=>data<=1023;
when 57=>data<=1023;
when 58=>data<=1023;
when 59=>data<=1023;
when 60=>data<=1023;
when 61=>data<=1023;
when 62=>data<=1023;
when 63=>data<=1023;
when others=>null;
end case;
end if;
end process;
end rtl;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -