?? fsq.fit.rpt
字號:
; 5 ; 3 ;
; 6 ; 5 ;
; 7 ; 3 ;
; 8 ; 5 ;
; 9 ; 9 ;
; 10 ; 48 ;
; 11 ; 9 ;
; 12 ; 5 ;
; 13 ; 6 ;
; 14 ; 3 ;
+---------------------------------------------+-------------------------------+
+---------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-------------------------------+
; Number of Signals Sourced Out (Average = 6.88) ; Number of LABs (Total = 106) ;
+-------------------------------------------------+-------------------------------+
; 0 ; 0 ;
; 1 ; 4 ;
; 2 ; 3 ;
; 3 ; 9 ;
; 4 ; 11 ;
; 5 ; 8 ;
; 6 ; 18 ;
; 7 ; 8 ;
; 8 ; 8 ;
; 9 ; 3 ;
; 10 ; 25 ;
; 11 ; 6 ;
; 12 ; 2 ;
; 13 ; 1 ;
+-------------------------------------------------+-------------------------------+
+------------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+-------------------------------+
; Number of Distinct Inputs (Average = 10.84) ; Number of LABs (Total = 106) ;
+----------------------------------------------+-------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 3 ;
; 4 ; 1 ;
; 5 ; 2 ;
; 6 ; 9 ;
; 7 ; 20 ;
; 8 ; 5 ;
; 9 ; 1 ;
; 10 ; 5 ;
; 11 ; 10 ;
; 12 ; 9 ;
; 13 ; 15 ;
; 14 ; 1 ;
; 15 ; 5 ;
; 16 ; 5 ;
; 17 ; 3 ;
; 18 ; 2 ;
; 19 ; 2 ;
; 20 ; 4 ;
; 21 ; 2 ;
+----------------------------------------------+-------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Dec 05 15:17:36 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off fsq -c fsq
Info: Selected device EPM1270T144C5 for design "fsq"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM570T144C5 is compatible
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144I5 is compatible
Info: Device EPM1270T144C5ES is compatible
Info: No exact pin location assignment(s) for 1 pins of 23 total pins
Info: Pin clk4 not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted some destinations of signal "clk" to use Global clock in PIN 18
Info: Destination "da_tran:u11|clk2" may be non-global or may not use global clock
Info: Automatically promoted signal "fp2:u2|outp" to use Global clock
Info: Automatically promoted some destinations of signal "fptd:u4|q" to use Global clock
Info: Destination "clk4" may be non-global or may not use global clock
Info: Destination "da_tran:u11|counter1[31]" may be non-global or may not use global clock
Info: Destination "fptd:u4|q" may be non-global or may not use global clock
Info: Destination "da_tran:u11|counter1[2]" may be non-global or may not use global clock
Info: Destination "da_tran:u11|counter1[3]" may be non-global or may not use global clock
Info: Destination "da_tran:u11|counter1[4]" may be non-global or may not use global clock
Info: Destination "da_tran:u11|process2~294" may be non-global or may not use global clock
Info: Destination "da_tran:u11|counter1[5]" may be non-global or may not use global clock
Info: Destination "da_tran:u11|counter1[6]" may be non-global or may not use global clock
Info: Destination "da_tran:u11|counter1[7]" may be non-global or may not use global clock
Info: Limited to 10 non-global destinations
Info: Automatically promoted some destinations of signal "da_tran:u11|dsclk" to use Global clock
Info: Destination "dsclk" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)
Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 19 total pin(s) used -- 7 pins available
Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 3 total pin(s) used -- 27 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 30 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 30 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:03
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to pin delay of 8.758 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y9; Fanout = 4; REG Node = 'da_tran:u11|counter1[6]'
Info: 2: + IC(1.073 ns) + CELL(0.740 ns) = 1.813 ns; Loc. = LAB_X13_Y9; Fanout = 1; COMB Node = 'da_tran:u11|process2~295'
Info: 3: + IC(1.673 ns) + CELL(0.740 ns) = 4.226 ns; Loc. = LAB_X14_Y10; Fanout = 1; COMB Node = 'da_tran:u11|process2~298'
Info: 4: + IC(0.896 ns) + CELL(0.740 ns) = 5.862 ns; Loc. = LAB_X15_Y10; Fanout = 12; COMB Node = 'da_tran:u11|process2~304'
Info: 5: + IC(0.574 ns) + CELL(2.322 ns) = 8.758 ns; Loc. = PIN_111; Fanout = 0; PIN Node = 'cs'
Info: Total cell delay = 4.542 ns ( 51.86 % )
Info: Total interconnect delay = 4.216 ns ( 48.14 % )
Info: Fitter placement operations ending: elapsed time is 00:00:36
Info: Fitter routing operations beginning
Info: Average interconnect usage is 20% of the available device resources. Peak interconnect usage is 21%.
Info: Fitter routing operations ending: elapsed time is 00:00:06
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Wed Dec 05 15:18:34 2007
Info: Elapsed time: 00:00:58
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