library ieee;
use ieee.std_logic_1164.All;

entity fptd is
  port( td1:in std_logic_vector(3 downto 0);
        clk: in std_logic;
        q:out std_logic);
end fptd;

architecture subdivision of fptd is

 signal a: integer range 0 to 1312;
begin
label1: process( td1)    
    begin
      case  td1 is
         when "0001" =>a<=1312;      --分頻得0.1HZ
         when "0010" =>a<=660;       --分頻得0.2HZ 
         when "0011" =>a<=440;       --分頻得 0.3HZ
         when "0100" =>a<=330;       --分頻得 0.4HZ
         when "0101" =>a<=260;       --分頻得 0.5HZ     
         when "0110"=> a<=220;       --分頻得 0.6HZ
         when "0111"=> a<=190;       --分頻得 0.7HZ
         when "1000"=> a<=160;       --分頻得 0.8HZ
         when "1001"=> a<=150;       --分頻得 0.9HZ
         when "1010"=> a<=130;       --分頻得 1HZ 
         when others=>null;
      end case;
    end process label1;

label2: process(clk)
    variable b,d: std_logic;
    variable c: integer range 0 to 1312;

   begin
        if clk'event and clk='1' then 
         if b='0' then
         c:=a-1;
         b:='1';
       else
         if c=1 then
            b:='0';
            d:=not d;
         else
            c:=c-1;
         end if;
       end if;
    end if;
     q<=d;
      end process label2;

end subdivision ;