LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fsq IS
PORT(
 clk:in std_logic;
 en :in std_logic;
  m,k,w1,w2: in std_logic;
  td1:in std_logic_vector(3 downto 0);
 cs,dsclk,din,clk4: out STD_LOGIC
 
);
END fsq;
ARCHITECTURE rtl OF fsq IS
signal asd :std_logic_vector(11 downto 0);
signal la,cs2,clk3:std_logic;
signal q3:std_logic_vector(9 downto 0);
signal q4:std_logic_vector(9 downto 0);
signal q5,q6:std_logic_vector(9 downto 0);
signal outbx:STD_LOGIC_VECTOR(9 DOWNTO 0);

component fptd 
PORT(
        td1:in std_logic_vector(3 downto 0);
        clk: in std_logic;
        q:out std_logic);
end component;


component zhengxuan 
PORT(clk:IN STD_LOGIC;
 outp: out STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END component;
component sanjiaobo
PORT(clk:IN STD_LOGIC; 
 outp: out STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END component;
component fangbo
PORT(clk:IN STD_LOGIC; 
 outp: out STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END component;
component ExpWave                                                    
  port(clk : in std_logic;
       outp: out std_logic_vector(9 downto 0));
END component;
component xb 
PORT(--clk:IN STD_LOGIC;
     clk,m,k,en,w1,w2: in std_logic;
     q,q1,q2,q3:in STD_LOGIC_VECTOR(9 DOWNTO 0);
 outp: out STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END component;
component da_tran
PORT(clk1:in STD_LOGIC;
     rst:in std_logic;
     qin:in std_logic_vector(9 downto 0);
 cs,dsclk: out STD_LOGIC
);
END component;
 component piso 
PORT(data :IN std_logic_vector(9 DOWNTO 0);
             sclk,sl : IN  std_logic;
			 q: OUT STD_LOGIC);
END component;
begin
cs<=cs2;
dsclk<=clk3;
clk4<=la;
u2:fptd
port map(td1,clk,la);
u3:zhengxuan
port map(la,q3);
u4:fangbo
port map(la,q4);
u5:sanjiaobo
port map(la,q5);
u6:ExpWave
port map(la,q6);
u7:xb
port map(clk,m,k,en,w1,w2,q3,q4,q5,q6,outbx);
u8:da_tran
port map(clk,la,outbx,cs2,clk3);
u9:piso
port map(outbx,clk3,cs2,din);

end rtl;