library ieee;
use ieee.std_logic_1164.All;

ENTITY piso IS
		PORT(data :IN std_logic_vector(9 DOWNTO 0);
             sclk,sl : IN  std_logic;
			 q: OUT   STD_LOGIC);
END piso;

ARCHITECTURE trl OF piso IS
	signal tmp : std_logic_vector(11 downto 0);
BEGIN
    process(sclk)
  begin 
    if sclk'event and sclk='0' then
      if sl='1' then 
  	     tmp(11)<=data(9);
  	     tmp(10)<=data(8);
  	     tmp(9)<=data(7);
  	     tmp(8)<=data(6);
  	     tmp(7)<=data(5);
  	     tmp(6)<=data(4);
 	     tmp(5)<=data(3);
  	     tmp(4)<=data(2);
 	     tmp(3)<=data(1);
 	     tmp(2)<=data(0);
		 tmp(1)<='0';
		 tmp(0)<='0';
      elsif sl='0' then
		q<=tmp(11);
     	for i in tmp'high downto tmp'low+1 loop
       		tmp(i)<=tmp(i-1);
    	end loop;	
      end if;
  end if;
end process;
end trl;