LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fangbo IS
PORT(clk:IN STD_LOGIC;
 outp: out STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END fangbo;
ARCHITECTURE rtl OF fangbo IS
signal l:integer range 63 downto 0;
--signal q:std_logic_vector(9 downto 0);
begin
process(clk)

begin
if clk'event and clk='1' then
  l<=l+1;
 if l>31 then
  outp<="1111111111";
 else 
  outp<="0000000000";
 end if;
end if;
end process;
end rtl;