LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY xb IS
PORT(
     clk,m,k,en,w1,w2: in std_logic;
     q,q1,q2,q3:in STD_LOGIC_VECTOR(9 DOWNTO 0);
 outp: out STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END xb;
ARCHITECTURE rtl OF xb IS
signal qwe1,qwe:integer;
signal cen,wave:std_logic_vector(1 downto 0);
signal outp1: STD_LOGIC_VECTOR(9 DOWNTO 0);
signal outp2: integer;
signal outp3: integer;
signal outp4: STD_LOGIC_VECTOR(9 DOWNTO 0);
begin
cen<=m&k;
wave<=w1&w2;
process(en)
begin
if clk'event and clk='1' then
if en='0' then
  outp<="0000000000";
else 
outp<=outp1;
end if;
end if;
end process;
process(cen)
begin
case cen is 
when"00"=>
 outp4<=q;
when"01"=>
 outp4<=q1;
when"10"=>
 outp4<=q2;
when"11"=>
 outp4<=q3;
when others=>null;
end case;
outp3<=conv_integer(outp4);
end process;
process(wave)
begin
case wave is
when"00"=>outp2<=outp3/2;
when"01"=>outp2<=outp3/4;
when"10"=>outp2<=outp3/8;
when"11"=>outp2<=outp3/16;
when others=>null;
end case;
outp1<=conv_std_logic_vector(outp2,10);
end process;
end rtl;