# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		fsq_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:01:00  NOVEMBER 14, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 5.1
set_global_assignment -name VHDL_FILE fangbo.vhd
set_global_assignment -name VHDL_FILE sanjiaobo.vhd
set_global_assignment -name VHDL_FILE zhengxuan.vhd
set_global_assignment -name VHDL_FILE fp.vhd
set_global_assignment -name VHDL_FILE td.vhd
set_global_assignment -name VHDL_FILE fsq.vhd
set_global_assignment -name VHDL_FILE xb.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE fsq.vwf
set_global_assignment -name VHDL_FILE da_tran.vhd
set_global_assignment -name VHDL_FILE piso.vhd
set_global_assignment -name VHDL_FILE fptd.vhd
set_global_assignment -name VHDL_FILE ExpWave.vhd
set_global_assignment -name VHDL_FILE fp1.vhd
set_global_assignment -name VHDL_FILE fp2.vhd
set_global_assignment -name VHDL_FILE timer.vhd
set_global_assignment -name VHDL_FILE mp.vhd

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_18 -to clk
set_location_assignment PIN_24 -to k
set_location_assignment PIN_27 -to m
set_location_assignment PIN_15 -to td1[0]
set_location_assignment PIN_14 -to td1[1]
set_location_assignment PIN_16 -to td1[2]
set_location_assignment PIN_21 -to td1[3]
set_location_assignment PIN_109 -to din
set_location_assignment PIN_111 -to cs
set_location_assignment PIN_110 -to dsclk
set_location_assignment PIN_1 -to en
set_location_assignment PIN_5 -to w1
set_location_assignment PIN_2 -to w2
set_location_assignment PIN_4 -to c1
set_location_assignment PIN_3 -to c2
set_location_assignment PIN_23 -to c3
set_location_assignment PIN_13 -to mk[1]
set_location_assignment PIN_12 -to mk[0]
set_location_assignment PIN_11 -to mp1[3]
set_location_assignment PIN_8 -to mp1[2]
set_location_assignment PIN_7 -to mp1[1]
set_location_assignment PIN_6 -to mp1[0]

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name TOP_LEVEL_ENTITY fsq

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EPM1270T144C5
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1