LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sanjiaobo IS
PORT(clk:IN STD_LOGIC; 
 outp: out STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END sanjiaobo;
ARCHITECTURE rtl OF sanjiaobo IS
signal l:integer range 63 downto 0;
signal q:std_logic_vector(9 downto 0);
begin
outp<=q;
process(clk)

begin

if clk'event and clk='1' then
  l<=l+1;
 if l<32 then
 if l=0 then
 q<=q+"100000";
 else 
 q<=q+"11111";
 end if;
  
 elsif l=63 then
 q<=q-"100000";
 else 
 q<=q-"11111";
 end if;
 end if;

end process;
end rtl;