LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY da_tran IS
PORT(clk1:in STD_LOGIC;
     cnt4:in std_logic;
     rst:in std_logic;
     qin:in std_logic_vector(9 downto 0);
 cs,dsclk: out STD_LOGIC
);
END da_tran;
architecture rtl of da_tran is
signal count:integer range 0 to 3;
signal counter:integer;
signal clk,clk2:std_logic;

signal clkout:std_logic;
begin
clk2<= clk1 and cnt4;
process(clk2)
begin 
	if(clk2'event and clk2='1') then
	if(count=5)then
			count<=0;
	else 
	
			count<=count+1;
		if (count<3) then
			clk<='0';
		else
			clk<='1';
		end if;
	end if;
	end if;
	dsclk<=clk;
end process;
process(rst,clk)
variable counter1:integer;
begin

if (clk'event and clk='1') then
if (rst='1')then

   counter1:=counter1+1;

else
counter1:=0;
end if;
end if;
counter<=counter1;
end process;
process(rst,counter)
begin

if counter<12 and rst='1' then
  cs<='0';
else
  cs<='1';

--else
--cs<='1';
end if;
end process;

end rtl;