?? asm_led.map.rpt
字號:
Analysis & Synthesis report for asm_led
Thu Apr 27 16:14:06 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis Equations
8. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Apr 27 16:14:05 2006 ;
; Quartus II Version ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name ; asm_led ;
; Top-level Entity Name ; asm_led ;
; Family ; MAX7000S ;
; Total macrocells ; 17 ;
; Total pins ; 19 ;
+-----------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+-----------------+---------------+
; Device ; EPM7128SLC84-15 ; ;
; Top-level entity name ; asm_led ; asm_led ;
; Family name ; MAX7000S ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
+----------------------------------------------------------------------+-----------------+---------------+
+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; asm_led.vhd ; yes ; User VHDL File ; G:/實驗4 呂/asm_led.vhd ;
; transform.vhd ; yes ; User VHDL File ; G:/實驗4 呂/transform.vhd ;
+----------------------------------+-----------------+-----------------+------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 17 ;
; Total registers ; 9 ;
; I/O pins ; 19 ;
; Shareable expanders ; 5 ;
; Maximum fan-out node ; x[3] ;
; Maximum fan-out ; 14 ;
; Total fan-out ; 142 ;
; Average fan-out ; 3.46 ;
+----------------------+----------------------+
+------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+-----------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+-----------------------+
; |asm_led ; 17 ; 19 ; |asm_led ;
; |transform:u1| ; 7 ; 0 ; |asm_led|transform:u1 ;
+----------------------------+------------+------+-----------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in G:/實驗4 呂/asm_led.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Thu Apr 27 16:14:04 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off asm_led -c asm_led
Info: Found 2 design units, including 1 entities, in source file asm_led.vhd
Info: Found design unit 1: asm_led-lightarch
Info: Found entity 1: asm_led
Info: Found 2 design units, including 1 entities, in source file transform.vhd
Info: Found design unit 1: transform-bav
Info: Found entity 1: transform
Info: Elaborating entity "asm_led" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at asm_led.vhd(39): signal "x" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "transform" for hierarchy "transform:u1"
Info: One or more bidirs are fed by always enabled tri-state buffers
Info: Fan-out of permanently enabled tri-state buffer feeding bidir "c[0]" is moved to its source
Info: Fan-out of permanently enabled tri-state buffer feeding bidir "c[1]" is moved to its source
Info: Fan-out of permanently enabled tri-state buffer feeding bidir "c[2]" is moved to its source
Info: Fan-out of permanently enabled tri-state buffer feeding bidir "c[3]" is moved to its source
Warning: Reduced register "c[3]~reg0" with stuck data_in port to stuck value GND
Warning: TRI or OPNDRN buffers permanently enabled
Warning: Node "c[0]~9"
Warning: Node "c[1]~10"
Warning: Node "c[2]~11"
Warning: Node "c[3]~12"
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: Implemented 41 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 13 output pins
Info: Implemented 4 bidirectional pins
Info: Implemented 17 macrocells
Info: Implemented 5 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
Info: Processing ended: Thu Apr 27 16:14:05 2006
Info: Elapsed time: 00:00:02
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