-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--x[3] is x[3] at LC56
x[3]_p1_out = x[1] & !x[2] & x[5] & x[0] & x[3] & x[4];
x[3]_or_out = x[3]_p1_out;
x[3]_reg_input = !(x[3]_or_out);
x[3] = DFFE(x[3]_reg_input, GLOBAL(clk), , , !reset);


--x[4] is x[4] at LC57
x[4]_p1_out = !x[3] & x[4] & x[0] & x[2] & x[1] & x[5];
x[4]_or_out = x[4]_p1_out;
x[4]_reg_input = !(x[4]_or_out);
x[4] = DFFE(x[4]_reg_input, GLOBAL(clk), , , !reset);


--x[1] is x[1] at LC51
x[1]_p1_out = x[2] & !x[0] & x[4] & x[3] & x[1] & x[5];
x[1]_or_out = x[1]_p1_out;
x[1]_reg_input = !(x[1]_or_out);
x[1] = DFFE(x[1]_reg_input, GLOBAL(clk), , , !reset);


--x[2] is x[2] at LC53
x[2]_p1_out = !x[1] & x[2] & x[5] & x[0] & x[3] & x[4];
x[2]_or_out = x[2]_p1_out;
x[2]_reg_input = !(x[2]_or_out);
x[2] = DFFE(x[2]_reg_input, GLOBAL(clk), , , !reset);


--A1L5Q is c[1]~reg0 at LC11
A1L5Q_p1_out = A1L5Q & reset;
A1L5Q_p2_out = !reset & x[1] & !x[2] & x[5] & x[0] & x[3] & x[4];
A1L5Q_p3_out = !reset & !x[1] & x[2] & x[5] & x[0] & x[3] & x[4];
A1L5Q_or_out = A1L5Q_p1_out # A1L5Q_p2_out # A1L5Q_p3_out;
A1L5Q_reg_input = A1L5Q_or_out;
A1L5Q = DFFE(A1L5Q_reg_input, GLOBAL(clk), , , );


--x[5] is x[5] at LC59
x[5]_p1_out = x[0] & x[2] & x[1] & x[5] & x[3] & !x[4];
x[5]_or_out = x[5]_p1_out;
x[5]_reg_input = !(x[5]_or_out);
x[5] = DFFE(x[5]_reg_input, GLOBAL(clk), , , !reset);


--A1L7Q is c[2]~reg0 at LC13
A1L7Q_p1_out = A1L7Q & reset;
A1L7Q_p2_out = !reset & x[0] & x[2] & x[1] & x[5] & !x[3] & x[4];
A1L7Q_p3_out = !reset & x[0] & x[2] & x[1] & x[5] & x[3] & !x[4];
A1L7Q_or_out = A1L7Q_p1_out # A1L7Q_p2_out # A1L7Q_p3_out;
A1L7Q_reg_input = A1L7Q_or_out;
A1L7Q = DFFE(A1L7Q_reg_input, GLOBAL(clk), , , );


--A1L25 is Mux~546 at SEXP57
A1L25 = EXP(x[5] & x[1] & x[2] & x[0] & !x[3] & x[4]);


--A1L26 is Mux~547 at SEXP56
A1L26 = EXP(x[5] & x[1] & x[2] & !x[0] & x[3] & x[4]);


--A1L27 is Mux~548 at SEXP53
A1L27 = EXP(x[5] & x[1] & x[2] & x[0] & x[3] & !x[4]);


--A1L28 is Mux~549 at SEXP49
A1L28 = EXP(x[5] & x[1] & !x[2] & x[0] & x[3] & x[4]);


--A1L29 is Mux~550 at SEXP51
A1L29 = EXP(x[5] & !x[1] & x[2] & x[0] & x[3] & x[4]);


--x[0] is x[0] at LC49
x[0]_p1_out = A1L25 & A1L26 & A1L27 & A1L28 & A1L29;
x[0]_or_out = x[0]_p1_out;
x[0]_reg_input = !(x[0]_or_out);
x[0] = DFFE(x[0]_reg_input, GLOBAL(clk), , , !reset);


--A1L3Q is c[0]~reg0 at LC14
A1L3Q_p1_out = A1L3Q & reset;
A1L3Q_p2_out = !reset & x[3] & x[1] & x[5] & !x[0] & x[2] & x[4];
A1L3Q_p3_out = !reset & x[3] & x[1] & x[5] & x[0] & x[2] & !x[4];
A1L3Q_p4_out = !reset & x[3] & x[1] & x[5] & x[0] & !x[2] & x[4];
A1L3Q_or_out = A1L3Q_p1_out # A1L3Q_p2_out # A1L3Q_p3_out # A1L3Q_p4_out;
A1L3Q_reg_input = A1L3Q_or_out;
A1L3Q = DFFE(A1L3Q_reg_input, GLOBAL(clk), , , );


--B1L4 is transform:u1|b[2]~473 at LC29
B1L4_p1_out = !A1L5Q & A1L7Q;
B1L4_or_out = B1L4_p1_out # A1L3Q;
B1L4 = !(B1L4_or_out);


--B1L1 is transform:u1|b[0]~477 at LC5
B1L1_p1_out = !A1L7Q & A1L5Q & !A1L3Q;
B1L1_or_out = B1L1_p1_out;
B1L1 = !(B1L1_or_out);


--B1L7 is transform:u1|b[6]~481 at LC8
B1L7_p1_out = !A1L5Q & A1L7Q & !A1L3Q;
B1L7_p2_out = !A1L5Q & !A1L7Q & A1L3Q;
B1L7_or_out = B1L7_p1_out # B1L7_p2_out;
B1L7 = !(B1L7_or_out);


--B1L3 is transform:u1|b[1]~486 at LC27
B1L3_p1_out = A1L5Q & !A1L7Q;
B1L3_p2_out = A1L5Q & A1L3Q;
B1L3_p3_out = !A1L7Q & A1L3Q;
B1L3_or_out = B1L3_p1_out # B1L3_p2_out # B1L3_p3_out;
B1L3 = !(B1L3_or_out);


--B1L5 is transform:u1|b[3]~491 at LC3
B1L5_p1_out = A1L5Q & A1L7Q & A1L3Q;
B1L5_p2_out = !A1L5Q & A1L7Q & !A1L3Q;
B1L5_p3_out = !A1L5Q & !A1L7Q & A1L3Q;
B1L5_or_out = B1L5_p1_out # B1L5_p2_out # B1L5_p3_out;
B1L5 = !(B1L5_or_out);


--B1L6 is transform:u1|b[5]~495 at LC6
B1L6_p1_out = A1L7Q & A1L5Q & !A1L3Q;
B1L6_p2_out = A1L7Q & !A1L5Q & A1L3Q;
B1L6_or_out = B1L6_p1_out # B1L6_p2_out;
B1L6 = !(B1L6_or_out);


--B1L2 is transform:u1|b[0]~500 at LC25
B1L2_p1_out = A1L7Q & !A1L5Q;
B1L2_p2_out = !A1L7Q & A1L5Q;
B1L2_p3_out = A1L5Q & !A1L3Q;
B1L2_or_out = B1L2_p1_out # B1L2_p2_out # B1L2_p3_out;
B1L2 = B1L2_or_out;


--~GND~0 is ~GND~0 at LC16
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--clk is clk at PIN_83
--operation mode is input

clk = INPUT();


--reset is reset at PIN_1
--operation mode is input

reset = INPUT();


--c[3] is c[3] at PIN_4
--operation mode is bidir

c[3]_open_drain_out = OPNDRN(~GND~0);
c[3] = BIDIR(c[3]_open_drain_out);


--catn[3] is catn[3] at PIN_37
--operation mode is output

catn[3] = OUTPUT(x[3]);


--catn[4] is catn[4] at PIN_36
--operation mode is output

catn[4] = OUTPUT(x[4]);


--catn[1] is catn[1] at PIN_40
--operation mode is output

catn[1] = OUTPUT(x[1]);


--catn[2] is catn[2] at PIN_39
--operation mode is output

catn[2] = OUTPUT(x[2]);


--catn[5] is catn[5] at PIN_35
--operation mode is output

catn[5] = OUTPUT(x[5]);


--c[1] is c[1] at PIN_8
--operation mode is bidir

c[1]_tri_out = TRI(A1L5Q, VCC);
c[1] = BIDIR(c[1]_tri_out);


--catn[0] is catn[0] at PIN_41
--operation mode is output

catn[0] = OUTPUT(x[0]);


--c[2] is c[2] at PIN_6
--operation mode is bidir

c[2]_tri_out = TRI(A1L7Q, VCC);
c[2] = BIDIR(c[2]_tri_out);


--d[2] is d[2] at PIN_15
--operation mode is output

d[2] = OUTPUT(B1L4);


--c[0] is c[0] at PIN_5
--operation mode is bidir

c[0]_tri_out = TRI(A1L3Q, VCC);
c[0] = BIDIR(c[0]_tri_out);


--d[4] is d[4] at PIN_11
--operation mode is output

d[4] = OUTPUT(B1L1);


--d[6] is d[6] at PIN_9
--operation mode is output

d[6] = OUTPUT(B1L7);


--d[0] is d[0] at PIN_17
--operation mode is output

d[0] = OUTPUT(B1L2);


--d[1] is d[1] at PIN_16
--operation mode is output

d[1] = OUTPUT(B1L3);


--d[3] is d[3] at PIN_12
--operation mode is output

d[3] = OUTPUT(B1L5);


--d[5] is d[5] at PIN_10
--operation mode is output

d[5] = OUTPUT(B1L6);