{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "10.529 ns register register " "Info: Estimated most critical path is register to register delay of 10.529 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ceping:inst\|min\[0\] 1 REG LAB_X23_Y9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X23_Y9; Fanout = 3; REG Node = 'ceping:inst\|min\[0\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "" { ceping:inst|min[0] } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/ceping.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.699 ns) + CELL(0.838 ns) 1.537 ns ceping:inst\|Add1~553 2 COMB LAB_X24_Y9 6 " "Info: 2: + IC(0.699 ns) + CELL(0.838 ns) = 1.537 ns; Loc. = LAB_X24_Y9; Fanout = 6; COMB Node = 'ceping:inst\|Add1~553'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.537 ns" { ceping:inst|min[0] ceping:inst|Add1~553 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/ceping.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.673 ns ceping:inst\|Add1~561 3 COMB LAB_X24_Y9 6 " "Info: 3: + IC(0.000 ns) + CELL(0.136 ns) = 1.673 ns; Loc. = LAB_X24_Y9; Fanout = 6; COMB Node = 'ceping:inst\|Add1~561'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.136 ns" { ceping:inst|Add1~553 ceping:inst|Add1~561 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/ceping.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.352 ns ceping:inst\|Add1~564 4 COMB LAB_X24_Y8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.679 ns) = 2.352 ns; Loc. = LAB_X24_Y8; Fanout = 2; COMB Node = 'ceping:inst\|Add1~564'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.679 ns" { ceping:inst|Add1~561 ceping:inst|Add1~564 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/ceping.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.233 ns) + CELL(0.114 ns) 3.699 ns ceping:inst\|min\[13\]~8884 5 COMB LAB_X24_Y9 1 " "Info: 5: + IC(1.233 ns) + CELL(0.114 ns) = 3.699 ns; Loc. = LAB_X24_Y9; Fanout = 1; COMB Node = 'ceping:inst\|min\[13\]~8884'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.347 ns" { ceping:inst|Add1~564 ceping:inst|min[13]~8884 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/ceping.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.212 ns) + CELL(0.442 ns) 4.353 ns ceping:inst\|min\[13\]~8885 6 COMB LAB_X24_Y9 7 " "Info: 6: + IC(0.212 ns) + CELL(0.442 ns) = 4.353 ns; Loc. = LAB_X24_Y9; Fanout = 7; COMB Node = 'ceping:inst\|min\[13\]~8885'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.654 ns" { ceping:inst|min[13]~8884 ceping:inst|min[13]~8885 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/ceping.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.905 ns) + CELL(0.442 ns) 5.700 ns ceping:inst\|min\[13\]~8887 7 COMB LAB_X25_Y8 7 " "Info: 7: + IC(0.905 ns) + CELL(0.442 ns) = 5.700 ns; Loc. = LAB_X25_Y8; Fanout = 7; COMB Node = 'ceping:inst\|min\[13\]~8887'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.347 ns" { ceping:inst|min[13]~8885 ceping:inst|min[13]~8887 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/ceping.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.212 ns) + CELL(0.442 ns) 6.354 ns ceping:inst\|Equal4~124 8 COMB LAB_X25_Y8 7 " "Info: 8: + IC(0.212 ns) + CELL(0.442 ns) = 6.354 ns; Loc. = LAB_X25_Y8; Fanout = 7; COMB Node = 'ceping:inst\|Equal4~124'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.654 ns" { ceping:inst|min[13]~8887 ceping:inst|Equal4~124 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/ceping.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.212 ns) + CELL(0.442 ns) 7.008 ns ceping:inst\|min\[19\]~8890 9 COMB LAB_X25_Y8 7 " "Info: 9: + IC(0.212 ns) + CELL(0.442 ns) = 7.008 ns; Loc. = LAB_X25_Y8; Fanout = 7; COMB Node = 'ceping:inst\|min\[19\]~8890'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.654 ns" { ceping:inst|Equal4~124 ceping:inst|min[19]~8890 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/ceping.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.212 ns) + CELL(0.442 ns) 7.662 ns ceping:inst\|min\[23\]~8892 10 COMB LAB_X25_Y8 7 " "Info: 10: + IC(0.212 ns) + CELL(0.442 ns) = 7.662 ns; Loc. = LAB_X25_Y8; Fanout = 7; COMB Node = 'ceping:inst\|min\[23\]~8892'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.654 ns" { ceping:inst|min[19]~8890 ceping:inst|min[23]~8892 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/ceping.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.114 ns) 8.316 ns ceping:inst\|min\[28\]~8894 11 COMB LAB_X25_Y8 7 " "Info: 11: + IC(0.540 ns) + CELL(0.114 ns) = 8.316 ns; Loc. = LAB_X25_Y8; Fanout = 7; COMB Node = 'ceping:inst\|min\[28\]~8894'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.654 ns" { ceping:inst|min[23]~8892 ceping:inst|min[28]~8894 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/ceping.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.114 ns) 8.970 ns ceping:inst\|min\[27\]~8906 12 COMB LAB_X25_Y8 3 " "Info: 12: + IC(0.540 ns) + CELL(0.114 ns) = 8.970 ns; Loc. = LAB_X25_Y8; Fanout = 3; COMB Node = 'ceping:inst\|min\[27\]~8906'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "0.654 ns" { ceping:inst|min[28]~8894 ceping:inst|min[27]~8906 } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/ceping.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.250 ns) + CELL(0.309 ns) 10.529 ns ceping:inst\|min\[26\] 13 REG LAB_X24_Y6 4 " "Info: 13: + IC(1.250 ns) + CELL(0.309 ns) = 10.529 ns; Loc. = LAB_X24_Y6; Fanout = 4; REG Node = 'ceping:inst\|min\[26\]'" {  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "1.559 ns" { ceping:inst|min[27]~8906 ceping:inst|min[26] } "NODE_NAME" } } { "ceping.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/ceping.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.514 ns ( 42.87 % ) " "Info: Total cell delay = 4.514 ns ( 42.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.015 ns ( 57.13 % ) " "Info: Total interconnect delay = 6.015 ns ( 57.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2_setup/win/TimingClosureFloorplan.fld" "" "10.529 ns" { ceping:inst|min[0] ceping:inst|Add1~553 ceping:inst|Add1~561 ceping:inst|Add1~564 ceping:inst|min[13]~8884 ceping:inst|min[13]~8885 ceping:inst|min[13]~8887 ceping:inst|Equal4~124 ceping:inst|min[19]~8890 ceping:inst|min[23]~8892 ceping:inst|min[28]~8894 ceping:inst|min[27]~8906 ceping:inst|min[26] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 3 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 3%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x14_y0 x27_y14 " "Info: The peak interconnect region extends from location x14_y0 to location x27_y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 02 15:02:45 2007 " "Info: Processing ended: Sun Dec 02 15:02:45 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/plvji.fit.smsg " "Info: Generated suppressed messages file F:/wangbin/例程/EDA實驗箱例程/程序/freqency/plvji.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}