{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 02 15:02:38 2007 " "Info: Processing started: Sun Dec 02 15:02:38 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off plvji -c plvji " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off plvji -c plvji" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ceping.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ceping.v" { { "Info" "ISGN_ENTITY_NAME" "1 ceping " "Info: Found entity 1: ceping" {  } { { "ceping.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/ceping.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "saomiao.v(24) " "Warning (10273): Verilog HDL warning at saomiao.v(24): extended using \"x\" or \"z\"" {  } { { "saomiao.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/saomiao.v" 24 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "saomiao.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file saomiao.v" { { "Info" "ISGN_ENTITY_NAME" "1 saomiao " "Info: Found entity 1: saomiao" {  } { { "saomiao.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/saomiao.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "select.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file select.v" { { "Info" "ISGN_ENTITY_NAME" "1 select " "Info: Found entity 1: select" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/select.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yima.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file yima.v" { { "Info" "ISGN_ENTITY_NAME" "1 yima " "Info: Found entity 1: yima" {  } { { "yima.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/yima.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "plvji.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file plvji.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 plvji " "Info: Found entity 1: plvji" {  } { { "plvji.bdf" "" { Schematic "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/plvji.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "plvji " "Info: Elaborating entity \"plvji\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "yima yima:inst3 " "Info: Elaborating entity \"yima\" for hierarchy \"yima:inst3\"" {  } { { "plvji.bdf" "inst3" { Schematic "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/plvji.bdf" { { 184 688 816 280 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "select select:inst2 " "Info: Elaborating entity \"select\" for hierarchy \"select:inst2\"" {  } { { "plvji.bdf" "inst2" { Schematic "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/plvji.bdf" { { 184 488 664 376 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "data1 select.v(10) " "Warning (10235): Verilog HDL Always Construct warning at select.v(10): variable \"data1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/select.v" 10 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "data2 select.v(11) " "Warning (10235): Verilog HDL Always Construct warning at select.v(11): variable \"data2\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/select.v" 11 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "data3 select.v(12) " "Warning (10235): Verilog HDL Always Construct warning at select.v(12): variable \"data3\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/select.v" 12 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "data4 select.v(13) " "Warning (10235): Verilog HDL Always Construct warning at select.v(13): variable \"data4\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/select.v" 13 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "data5 select.v(14) " "Warning (10235): Verilog HDL Always Construct warning at select.v(14): variable \"data5\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/select.v" 14 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "data6 select.v(15) " "Warning (10235): Verilog HDL Always Construct warning at select.v(15): variable \"data6\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/select.v" 15 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "data7 select.v(16) " "Warning (10235): Verilog HDL Always Construct warning at select.v(16): variable \"data7\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "select.v" "" { Text "F:/wangbin/例程/EDA實驗箱例程/程序/freqency/select.v" 16 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}